Hardware Description Languages — Tier 3 Index
Hardware Description Languages — Tier 3 Index
- Type: Family index (Tier 3)
- Family: Hardware Description Languages (HDLs) and High-Level Synthesis
- Languages catalogued: 17 (plus 2 ecosystem tools)
- Last updated: 2026-05-07
Family overview
Hardware Description Languages describe digital circuits at register-transfer or behavioural levels for simulation, synthesis to gates, and formal verification. The field bifurcates into the IEEE-standard mainstream (Verilog, SystemVerilog, VHDL — what every commercial ASIC and most FPGAs ship in) and a long tail of embedded HDLs that host hardware semantics inside a general-purpose host language (Scala for Chisel/SpinalHDL, Python for Amaranth/MyHDL/Magma/PyMTL, Haskell for Clash). A third axis — High-Level Synthesis (HLS) — compiles annotated C/C++/SystemC down to RTL and has slowly become production-credible at Xilinx/AMD, Intel, and Siemens EDA. The EDA tooling itself is overwhelmingly driven by Tcl glue scripts, which is why Tcl persists as a load-bearing language in any serious chip-design flow.
In our deep library
No deep notes yet for this family. Closest cross-links:
- scala — host for Chisel and SpinalHDL
- python — host for Amaranth, MyHDL, Magma, PyMTL
- haskell — host for Clash
- tcl — the scripting layer of every major EDA tool
- concurrency-and-actors — OCCAM/CSP lineage
Tier 3 — the family
| Language | First release | Status 2026 | Niche | Why it matters | Source URL |
|---|---|---|---|---|---|
| Verilog | 1984 | Standard (IEEE 1364) | RTL design, ASIC/FPGA | The lingua franca of digital design; foundation Cadence built on | https://en.wikipedia.org/wiki/Verilog |
| SystemVerilog | 2005 (IEEE 1800) | Dominant verification standard | RTL + verification (UVM) | Verilog superset with classes, assertions, constrained random — UVM testbenches are written here | https://en.wikipedia.org/wiki/SystemVerilog |
| VHDL | 1987 (IEEE 1076) | Standard, Europe/defense-heavy | RTL design | DoD-pushed Ada-flavoured alternative to Verilog; strong typing, popular in aerospace/defense and EU FPGA shops | https://en.wikipedia.org/wiki/VHDL |
| SystemC | 2000 (IEEE 1666) | Living, HLS+TLM | Transaction-level modeling, HLS | C++ class library for system-level models and HLS input; Accellera-stewarded | https://systemc.org/ |
| Bluespec (BSV) | 2000 | Niche but active; open-sourced 2020 | High-assurance, RISC-V | Guarded atomic actions from MIT; Haskell-flavoured; underpins parts of the open RISC-V ecosystem | https://github.com/B-Lang-org/bsc |
| Chisel | 2012 | Active (UCB/SiFive) | Agile RTL, RISC-V | Scala-embedded; emits FIRRTL IR; underpins SiFive cores and Chipyard | https://www.chisel-lang.org/ |
| SpinalHDL | 2015 | Active community | Pragmatic Scala HDL | Scala-embedded alternative to Chisel; richer built-in libraries, friendlier waveform/debug story | https://spinalhdl.github.io/SpinalDoc-RTD/ |
| Amaranth (ex-nMigen) | 2020 (renamed) | Active (LibreSilicon, ymmv) | Python-embedded HDL | Successor to Migen; clean Python DSL, good open-toolchain (Yosys) integration | https://amaranth-lang.org/ |
| Migen | 2011 | Superseded by Amaranth | Python-embedded HDL | Predecessor to Amaranth; still in some legacy SoC repos (M-Labs, LiteX origin) | https://github.com/m-labs/migen |
| MyHDL | 2003 | Maintenance | Python-embedded HDL | Pioneer of Python-as-HDL; uses generators for concurrent processes; converts to Verilog/VHDL | http://www.myhdl.org/ |
| Magma | 2017 | Active research | Python-embedded HDL | Stanford project; emphasis on circuit-as-function and metaprogramming | https://github.com/phanrahan/magma |
| PyMTL / PyMTL3 | 2014 | Active (Cornell) | Python-embedded HDL + simulation | Cornell Batten group; integrates simulation, RTL, and Verilog co-sim | https://pymtl.csl.cornell.edu/ |
| Clash | 2010 | Active | Haskell-embedded HDL | Pure functional HDL; types-as-circuits; compiles to Verilog/VHDL/SystemVerilog | https://clash-lang.org/ |
| Handel-C | 1996 | Defunct | Historical C-to-hardware | Oxford/Celoxica; one of the first C-syntax HDLs; influenced modern HLS | https://en.wikipedia.org/wiki/Handel-C |
| OCCAM | 1983 | Historical | Transputer / CSP ancestor | Hoare’s CSP made executable on INMOS Transputers; intellectual ancestor of Go channels | https://en.wikipedia.org/wiki/Occam_(programming_language) |
| Vivado HLS / Vitis HLS | 2011 | Active (AMD/Xilinx) | C/C++ → RTL for FPGA | Mainstream HLS path on AMD FPGAs; pragmas drive pipelining/unrolling | https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis/vitis-hls.html |
| Catapult HLS | 2004 | Active (Siemens EDA) | C++/SystemC → RTL for ASIC | Long-running HLS for ASIC flows; strong constraint-driven scheduling | https://eda.sw.siemens.com/en-US/ic/catapult-high-level-synthesis/ |
| Intel HLS / oneAPI FPGA | 2017 | Folded into oneAPI | SYCL/DPC++ → FPGA | Intel pivoted from standalone HLS to SYCL-based oneAPI flow | https://www.intel.com/content/www/us/en/developer/tools/oneapi/fpga.html |
Ecosystem tools (not languages, but load-bearing)
| Tool | Role | URL |
|---|---|---|
| Verilator | Cycle-accurate Verilog→C++ simulator; the open-source workhorse | https://www.veripool.org/verilator/ |
| Yosys | Open-source Verilog synthesis (and SystemVerilog subset); core of the open FPGA toolchain | https://yosyshq.net/yosys/ |
| Tcl | The actual interface to Vivado, Quartus, Innovus, Design Compiler, PrimeTime — every EDA tool exposes its API as Tcl | https://en.wikipedia.org/wiki/Tcl |
Notable threads
The Scala/Python embedded-HDL movement. Around 2010 a wave of academic groups (UCB, MIT, Stanford, Cornell, M-Labs) decided that writing RTL in 1984-vintage Verilog was holding back hardware productivity the same way Cobol held back software. Their bet: host an HDL inside a modern language with first-class generics, type inference, and unit-testing tools. Chisel (Scala) won the headline brand by powering SiFive’s commercial RISC-V cores, but the same idea recurred in Amaranth (Python), Clash (Haskell), and SpinalHDL (Scala, more pragmatic). Adoption in industry remains uneven — most production ASIC teams still write SystemVerilog because their EDA contracts and verification IP demand it — but the open-source RISC-V world is overwhelmingly Chisel/SpinalHDL/Bluespec.
HLS finally working. For thirty years “C-to-gates” was a punchline. Around 2015 the combination of (a) AMD/Xilinx subsidising HLS for their FPGAs, (b) the rise of streaming/dataflow workloads (video, ML inference, networking) that match HLS’s strengths, and (c) better scheduling algorithms made Vivado/Vitis HLS and Catapult HLS production-grade for some problem classes. It’s still bad at general-purpose CPU control logic, but for image pipelines, ML accelerators, and protocol offloads it’s now competitive with hand-written RTL on time-to-market.
OCCAM’s long shadow. OCCAM ran on the INMOS Transputer in the 1980s — a microprocessor designed around CSP message-passing. The hardware lost the commercial battle but the language model (channels, ALT, parallel composition) reappeared everywhere: Go’s channels, Erlang’s mailboxes, Limbo, Newsqueak, Plan 9. The HDL world keeps the OCCAM lineage alive through Bluespec’s guarded atomic actions and the broader idea that hardware concurrency wants different primitives than threads-with-locks. Cross-link: concurrency-and-actors.
Tcl’s surprising durability. Tcl is regularly mocked as a “1990s scripting curio,” but every major EDA tool — Vivado, Quartus, Synopsys Design Compiler, Cadence Innovus, Mentor Questa — exposes its automation surface as a Tcl interpreter. A working chip designer in 2026 writes more Tcl than they’d care to admit. Replacing it would require coordinated migration across vendors that nobody has commercial incentive to fund.
Citations
- IEEE 1364 (Verilog): https://standards.ieee.org/ieee/1364/2052/
- IEEE 1800 (SystemVerilog): https://standards.ieee.org/ieee/1800/7743/
- IEEE 1076 (VHDL): https://standards.ieee.org/ieee/1076/7027/
- IEEE 1666 (SystemC): https://standards.ieee.org/ieee/1666/4814/
- Bluespec open-source compiler: https://github.com/B-Lang-org/bsc
- Chisel: https://www.chisel-lang.org/
- SpinalHDL: https://spinalhdl.github.io/SpinalDoc-RTD/
- Amaranth: https://amaranth-lang.org/
- MyHDL: http://www.myhdl.org/
- Clash: https://clash-lang.org/
- Verilator: https://www.veripool.org/verilator/
- Yosys: https://yosyshq.net/yosys/
- Vitis HLS: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis/vitis-hls.html
- Catapult HLS: https://eda.sw.siemens.com/en-US/ic/catapult-high-level-synthesis/
- OCCAM/CSP background: https://en.wikipedia.org/wiki/Occam_(programming_language)