Compendium

Semiconductor Materials and Process Deep

25 min read

Semiconductor Materials and Process Deep

A Tier 2 deep-dive into the materials, chemistries, and process integration of the semiconductor industry — silicon and compound-semiconductor wafers; lithography resists and EUV pellicles; etch/deposition/CMP gas and slurry chemistry; ALD/CVD precursors; FinFET-to-GAA-nanosheet device materials; advanced-packaging substrates and interconnect (CoWoS, EMIB, SoIC, FOWLP, glass core); MEMS structural and piezoelectric materials; and the emerging-memory roadmap (FeRAM, MRAM, RRAM, PCM). Modern logic and memory are produced by an interlocking supply chain spanning monolithic crystal growth (Shin-Etsu, SUMCO), photoresists (JSR, TOK, Shin-Etsu), specialty gases (Linde, Air Liquide, Air Products, Versum/Merck, SK Materials), and process tools (ASML, Applied Materials, LAM, TEL, KLA). With high-NA EUV at TSMC and Intel, backside power delivery on Intel 18A and Samsung SF2, and 2 nm nanosheet ramp at TSMC N2 in 2025-2026, materials innovation now defines the leading-edge node more than tool throughput.

See also

Substrate wafers

Monocrystalline silicon

Czochralski (CZ) growth: high-purity polysilicon (Siemens process from SiHCl3) melted in fused-silica crucible at 1414 °C under Ar atmosphere; <100>-, <110>-, or <111>-oriented seed crystal dipped into melt, slowly rotated and withdrawn at 0.5-2 mm/min to grow ingot 100-450 mm diameter, 1-3 m long.

  • 300 mm wafers (12-inch) are the standard for advanced logic + memory since ~2002. ITRS roadmap for 450 mm (18-inch) wafers stalled around 2014 — Intel/TSMC/Samsung G450C consortium dissolved 2017; capex per shrink + lack of supplier consensus killed the transition.
  • 200 mm (8-inch) wafers remain dominant for automotive analog, power, RF, and MEMS — supply shortage 2020-2023 driven by automotive demand triggered global semiconductor crisis.
  • 150 mm (6-inch) and 125 mm (5-inch) still in use for legacy fabs and compound semiconductors.

Float zone (FZ) growth: no crucible — polysilicon rod melted by RF induction in a moving zone; the melt is held by surface tension. Eliminates oxygen contamination from the silica crucible. Used for ultra-pure / high-resistivity silicon (>1000 Ω·cm) for IGBT power devices, neutron detectors, and high-Q RF passives. Topsil (acquired by GlobalWafers 2016) was the historic FZ leader; Siltronic, SUMCO, Shin-Etsu now offer FZ portfolios.

Grades:

  • Prime — pristine surface, used for actual device fabrication.
  • Test — used to qualify processes and tools (slightly out-of-spec on flatness or particles).
  • Monitor — single-use process monitor wafers.
  • ULSI (ultra-large-scale integration) grade — sub-1 ppba metallic contamination; <0.1 defects/cm2.
  • Epitaxy wafers — CVD-grown 1-50 µm epi layer on CZ substrate, dopant graded for vertical power devices, BiCMOS, image sensors.

SOI (silicon-on-insulator)

Insulated thin silicon device layer (10-200 nm) on buried oxide (BOX, 10-400 nm SiO2) on bulk silicon handle (~775 µm).

  • Smart Cut (Bruel 1995, Soitec patent) — H+ implantation into oxidized donor wafer creates fracture plane; wafer bonded to handle; thermal annealing cleaves at H plane. Industrial workhorse since ~2000. Soitec (Bernin France) the dominant supplier; SEH Smart Stacking, SUMCO, Simgui (China) alternatives. Soitec 2024 revenue ~1 B EUR, mostly SOI + GaN-on-Si + InP-on-Si.
  • BESOI (bonded etch-back SOI) — original technique, lower yield.
  • SIMOX (separation by implantation of oxygen) — high-dose O+ implant + anneal forms buried oxide in situ; superseded by Smart Cut.

Variants:

  • FD-SOI (fully-depleted SOI) — device-layer Si thinned to ~6-12 nm; channel fully depleted; lower variability + back-gate biasing for power management. GlobalFoundries 22FDX + 12FDX nodes; STMicroelectronics + NXP automotive + IoT customers. Samsung 28FDS legacy.
  • PD-SOI (partially-depleted SOI) — thicker device layer (~50-100 nm); some bulk-Si-like behavior; IBM POWER processors used until POWER10 (2021).
  • RF-SOI — high-resistivity handle wafer (>1 kΩ·cm), used for RF front-end modules (Qorvo, Skyworks, Murata) — every modern smartphone has multiple RF-SOI dice.
  • Imager-SOI — back-side-illuminated CMOS image sensors (Sony Exmor R since 2008 — first commercial BSI in Cybershot DSC-HX5V).
  • FD-SOI on 300 mm at 22 nm (GF 22FDX) and 12 nm (GF 12FDX) — currently the most advanced FD-SOI node in production.

GeOI (germanium-on-insulator): Ge device layer for high-mobility n/p-MOSFETs; research-stage at IMEC and CEA-Leti.

III-V compound semiconductors

  • GaAs (gallium arsenide) — bandgap 1.42 eV; LO-phonon-limited electron mobility 8500 cm2/V·s. LEDs, laser diodes (CD/DVD), HEMT (high electron mobility transistor) for RF — Qorvo, Wolfspeed, MACOM, MicroSemi (Microchip). 4-6-inch wafers standard; Freiberger Compound Materials, AXT, Sumitomo Electric, II-VI/Coherent suppliers.
  • GaN-on-SiC — GaN epi (HEMT) on semi-insulating SiC handle. RF power amplifiers for 4G/5G base stations, military radar, satcom. Qorvo, Wolfspeed RFGaN, Sumitomo Electric Devices Innovations.
  • GaN-on-Si — power applications 100-650 V (consumer fast chargers, datacenter PSUs, EV onboard charger). Navitas (Nasdaq: NVTS), GaN Systems (acquired by Infineon Sep 2023 for $830M), Power Integrations InnoSwitch3, EPC (Efficient Power Conversion), Innoscience (China), Transphorm. Currently 150 mm + 200 mm; 300 mm in development (Intel + IMEC).
  • GaN-on-sapphire — LED epi standard (blue/white LEDs); Lumileds, OSRAM, Cree-LED (Smart Global Holdings since 2021), Nichia, Seoul Semiconductor.
  • InP (indium phosphide) — bandgap 1.35 eV; optoelectronics for telecom (1.3, 1.55 µm lasers + photodetectors), HBT (heterojunction bipolar transistor) for high-frequency RF (>100 GHz). Coherent, Sumitomo Electric, AXT, IQE epi-wafer services. 3-4-inch standard; 6-inch emerging (Coherent 2024).
  • InGaAs/InAlAs — HEMT/HBT epi layers on InP for mm-wave (60-300 GHz) — radio astronomy, 6G research, automotive radar.
  • GaSb — mid-IR detectors and lasers (2-5 µm).

SiC (silicon carbide)

Wide-bandgap (3.26 eV 4H polytype), thermal conductivity 4.9 W/cm·K, breakdown field ~3 MV/cm — power device material of choice for 600-3300 V applications (EV traction inverters, solar PV inverters, fast chargers).

PVT (physical vapor transport, modified Lely method) — sublimation growth at 2200-2400 °C in graphite crucible; growth rate ~0.3-0.5 mm/h; ingots 50-150 mm diameter, 30-50 mm tall.

200 mm SiC wafer transition 2024-2026:

  • Wolfspeed (Durham NC; renamed from Cree 2021) — Mohawk Valley NY fab opened April 2022 as the first 200 mm SiC fab; supply ramp constrained by financial and yield issues 2024-2025 (Chapter 11 filing avoided but workforce cuts + capex pullback).
  • STMicroelectronics — Catania Italy 200 mm SiC fab opened 2023; expanded partnership with Soitec for SmartSiC (engineered SiC substrate combining poly-SiC handle + thin monocrystalline SiC layer via Smart Cut — Soitec licensed by ST 2022).
  • Onsemi (Hudson NH + Bucheon Korea + Czech Republic) — acquired GTAT 2021 for boule production; now vertically integrated. Volkswagen ID series partnership 2023.
  • Coherent II-VI (Saxonburg PA) — historic II-VI Inc; 200 mm SiC ramp 2024-2025.
  • Resonac (Showa Denko) — Japanese SiC epi wafer supplier.
  • SK Siltron CSS (acquired DuPont SiC 2020) — Korean major.
  • Soitec SmartSiC — engineered substrate enabling SiC device on poly-SiC handle, reducing crystalline SiC consumption by ~10×.

Other emerging substrates

  • Ga2O3 (gallium oxide) — ultra-wide bandgap 4.8 eV; potential beyond SiC/GaN for >5 kV. Novel Crystal Technology (Japan, NCT), Kyma Technologies (US). EFG (edge-defined film-fed growth) ingots; melt-grown via Czochralski with iridium crucible. Research-stage.
  • AlN (aluminum nitride) — bandgap 6.2 eV; deep-UV LEDs (water purification). Hexatech, Crystal IS, Asahi Kasei.
  • Diamond — ultimate wide-bandgap (5.47 eV); thermal management substrate (Element Six, Diamond Foundry, AKHAN Semi). CVD diamond on Si/SiC heat-spreader integration.
  • 2D materials — MoS2, WS2, WSe2, graphene as transistor channel; research-stage at IMEC, CEA-Leti, TSMC, Samsung 2D process integration consortia.

Photolithography materials

DUV (193 nm + 248 nm)

  • KrF excimer (248 nm) — introduced ~250 nm node (1995). Hardly used for leading-edge logic but still ubiquitous for memory periphery, displays, mid-range nodes (40-90 nm).
  • ArF excimer (193 nm) — introduced ~130 nm node. ArF dry until 65 nm; ArF immersion (water at 193 nm gives effective lambda ~134 nm with NA up to 1.35) from 45 nm to current EUV nodes. Multiple-patterning (LELE, LFLE, SADP/SAQP) extended ArFi to 7 nm + 5 nm logic.

ArF photoresist suppliers — fragmented among Japanese specialists:

  • JSR Corporation (Tokyo; bought by JIC + Bain 2024) — ~30% market share; ARX, MX series.
  • Shin-Etsu Chemical — SAIL series.
  • Tokyo Ohka Kogyo (TOK) — TARF series.
  • Sumitomo Chemical — SUMIRESIST.
  • Dongjin Semichem (Korea) — Asian fab supplier.
  • DuPont/Merck KGaA — broader specialty portfolio.

Chemical structure: ArF resists use polyhydroxystyrene + methacrylate copolymers with photoacid generators (PAG — onium salts: triphenylsulfonium triflate, diphenyliodonium nonaflate). Acid-catalyzed deprotection of protecting groups (t-butyl ester, acetal) drives solubility switch.

EUV (13.5 nm)

ASML EUV lithography uses laser-produced Sn-droplet plasma source (Cymer/Trumpf collaboration) emitting 13.5 nm photons; 6-mirror reflective Schwarzschild optics; NA 0.33 (standard EUV) / 0.55 (high-NA EUV, NXE:5000 series TWINSCAN). First commercial EUV layer: TSMC N7+ (2019); first majority-EUV node: TSMC N5 (2020); current: TSMC N3, N2 + Samsung SF3/SF2 + Intel 18A.

EUV resists:

  • CAR (chemically amplified resists) — extension of DUV chemistry to 13.5 nm. JSR + Inpria-merger (JSR acquired Inpria 2021 for $514M), TOK, Shin-Etsu. CAR limited by stochastic effects + LWR (line-width roughness) at sub-30 nm.
  • Metal-oxide resists (MOR) — Inpria-developed (acquired by JSR 2021). Tin-oxide-cluster cage molecules (e.g., (BuSn)12O14(OH)6^2+) cross-link via EUV photochemistry. High EUV absorption coefficient (~5× higher than CAR), narrower LWR, lower dose. Now used in production at TSMC N3 + Samsung SF3 + Intel 18A.
  • Lam Photochemistry (formerly RAPT) — dry-deposited EUV resists by ALD-type vapor process. R&D-stage with TSMC.

EUV pellicles — protective membranes covering photomask, preventing falling particles from imaging onto wafer:

  • Polysilicon-based (Mitsui Chemicals, ASML) — first-gen EUV pellicles, ~70% transmission.
  • CNT-based (Imec + Canatu) — higher transmission >88%, can withstand higher source power.
  • High-NA EUV pellicle constraints — wider angular range + thinner membrane required; multiple suppliers in qualification 2024-2025.

EUV mask blanks — Mo/Si multilayer (~40 bilayers, 6.7 nm period) on low-thermal-expansion glass (LTEM, Schott Zerodur or Corning ULE). Suppliers: HOYA, AGC, S&S Tech (Korea).

EUV photomasks — patterned absorber (TaN, TaBN, Ru/RuTa, low-thickness ALD): blank suppliers + mask shops Toppan + DNP + Photronics. Cost $0.3M-$3M per high-end EUV mask depending on layer count + complexity; full TSMC N3 mask set ~$30M.

Etch and deposition gas chemistry

Etch gases

  • NF3 (nitrogen trifluoride) — clean-gas workhorse for chamber clean after dep/etch + remote-plasma source for selective W/TiN strip. SK Materials (Korea), Versum/Merck, Foosung. SK Materials is the world’s largest NF3 producer; capacity expansion 2023-2024.
  • WF6 (tungsten hexafluoride) — W metal-fill CVD precursor (interconnect plugs, gates). Linde, Air Products, SK Materials.
  • C4F8, C4F6, CF4, CHF3, CH2F2 — fluorocarbon etch chemistry for dielectric (oxide, nitride) — generates polymer passivation on sidewalls for anisotropic etch.
  • Cl2, BCl3, HBr — Si etch (poly-Si gate, recess), Al etch (legacy).
  • HBr (hydrogen bromide) — high-aspect-ratio Si etch (FinFET fin formation, DRAM contact, NAND channel).
  • SF6 (sulfur hexafluoride) — isotropic Si etch (Bosch process for MEMS); high global warming potential → driving substitution research.
  • CO/COS — selective metal removal.
  • O2, H2, NH3, N2 — plasma processing.
  • Ar, He, Xe — sputter, dilution, momentum transfer.

Specialty gas supply chain: Linde Engineering, Air Liquide Electronics, Air Products (now Versum/Merck post-2019 acquisition), Showa Denko (now Resonac), Taiyo Nippon Sanso, Kanto Denka Kogyo, SK Materials, Foosung. Industry highly concentrated; capacity tight 2023-2025 after Ukraine war (neon, Ar, Kr from Mariupol affected).

CMP slurries (chemical-mechanical planarization)

Slurry = abrasive (silica, alumina, ceria) + oxidant (H2O2, KIO3, NH4OH) + chelator + pH buffer + surfactant.

  • Oxide CMP — silica or ceria abrasive in alkaline carrier; STI (shallow trench isolation), ILD (inter-layer dielectric).
  • W CMP — silica + H2O2 + ferric nitrate inhibitor; tungsten plug planarization.
  • Cu CMP — alumina or silica + H2O2 + BTA (benzotriazole) corrosion inhibitor + chelator; Damascene copper interconnect.
  • Co CMP — H2O2 + glycine + BTA; cobalt fill at 7 nm + 5 nm node.
  • Ru CMP — emerging at 3 nm + 2 nm for barrier-free interconnect; corrosive chemistries with NaOCl + H5IO6.

Suppliers: CMC Materials (acquired Entegris 2022, $6B deal), DuPont Electronics & Industrial (post-DuPont/Dow merger), Versum/Merck KGaA, Fujimi, Showa Denko/Resonac, Cabot Microelectronics (renamed CMC), KCTech (Korea).

CVD/ALD precursors

ALD (atomic layer deposition) discovered 1974 by Tuomo Suntola (VTT Finland; first patent FI 52780 1977) for electroluminescent flat-panel display thin-films; rediscovered for semiconductor logic at HKMG (high-k metal gate) introduction at Intel 45 nm (2007). Self-limiting sequential half-reactions enable Å-level thickness control + perfect conformality on high-aspect-ratio features.

Key ALD precursors:

  • TMA (trimethylaluminum, Al(CH3)3) — Al2O3 with H2O. Workhorse “binary” demo precursor; used in DRAM capacitor stacks, HKMG.
  • TDMAT (tetrakis(dimethylamino)titanium) — TiN with NH3, TiO2 with H2O/O3.
  • TDMAH (tetrakis(dimethylamino)hafnium) — HfO2 high-k gate dielectric with O3 or H2O. HKMG enabler at Intel 45 nm (2007).
  • HCDS (hexachlorodisilane, Si2Cl6) — SiN, SiON, SiO2 (with various co-reactants). Used in NAND ONO stacks + spacer dielectric.
  • TEOS (tetraethyl orthosilicate) — SiO2 CVD precursor (legacy; superseded by ALD for thin layers).
  • BTBAS (bis(t-butylamino)silane) — SiO2 ALD precursor.
  • WF6 — W ALD plug fill, with SiH4 or B2H6 nucleation.
  • Pt(MeCp)Me3 — Pt ALD for high-work-function metals + MEMS electrodes.
  • Co(MeCp)2 — Co fill at 7 nm/5 nm interconnect plug + selective Co growth.
  • Ru(EtCp)2 — Ru ALD for emerging barrier-less interconnect; PMC Group, Air Liquide.

Suppliers: Air Liquide Specialty (Voltaix legacy), Versum/Merck (organometallic specialties), DNF (Korea), SoulBrain (Korea), JNC, ADEKA, Strem Chemicals, Tanaka Kikinzoku.

Tool ALD vendors: ASMI (ASM International, Almere NL — pulsed-CVD ALD pioneer), Applied Materials Centura/Endura ALD modules, LAM Research SABRE/VECTOR, TEL Trias, Wonik IPS (Korean DRAM specialist), Hitachi High-Tech.

Front-end-of-line (FEOL) device materials

FinFET (22 nm to 5 nm, 2011-2022)

3D fin geometry replacing planar MOSFET at 22 nm (Intel Ivy Bridge 2011) → 14 nm (Broadwell 2014) → 10 nm/7 nm/5 nm continuation at Intel + TSMC + Samsung + GF (GF stopped at 14 nm 2018).

Fin material: bulk Si or strained Si. Source-drain epi: SiGe (PMOS, induces compressive strain) + Si:P (NMOS, induces tensile strain). Gate stack: TiN/TaN work-function metals on HfO2 high-k dielectric.

GAA nanosheet (3 nm onward)

Gate-all-around horizontal nanosheet stack: 2-3 silicon channel sheets, ~6-8 nm thick, separated by SiGe sacrificial layers that are etched out after channel patterning. Gate surrounds each sheet. Improves short-channel control beyond FinFET.

  • Samsung 3nm GAA “MBCFET” (multi-bridge channel FET) — first GAA in production June 2022.
  • TSMC N2 (2 nm) — GAA nanosheet expected 2025 production ramp.
  • Intel 20A/18A — RibbonFET nanosheet + PowerVia backside power delivery, first products Q4 2025 (Panther Lake mobile, Clearwater Forest server).
  • TSMC N1.4 and beyond — 2027+ further nanosheet refinements; forksheet (IMEC concept), CFET (complementary FET stacking N over P).

Backside power delivery (BSPDN)

Power rails moved from front-side metal stack to backside of thinned wafer. Frees front-side routing congestion + reduces IR drop on long power rails.

  • Intel PowerVia — first commercial BSPDN; demonstrated on Intel 4 test chip (2023); production at Intel 20A/18A (2025).
  • TSMC SPR (super power rail) — BSPDN at N2P (2026).
  • Samsung — BSPDN at SF2P (2026-2027).

Materials challenges: TSV (through-silicon via) keep-out zones, backside passivation, thin-wafer handling, bonded handle wafer techniques (carrier wafers from Ferrotec, EVG bonders).

High-k metal gate (HKMG)

HfO2-based high-k replaces SiO2 gate dielectric to reduce leakage; metal gate replaces poly-Si for work-function tuning. Introduced Intel 45 nm (Penryn 2007) with HfO2 + TiN/TiAl + Al fill. Refinements: HfSiO with various dopants (La, Mg, Y, Al for work-function tuning), Hf-based ALD precursors at 5 nm + 3 nm.

Strained-Si engineering

  • eSiGe (embedded SiGe) S/D in PMOS — compressive strain, +30-50% hole mobility.
  • Si:P S/D in NMOS — tensile strain, +10-20% electron mobility.
  • SiC (carbon-doped silicon, dilute substitutional C) — alternate NMOS S/D strain.
  • Process-induced strain from nitride contact-etch-stop liners (CESL).

Channel materials beyond Si

  • SiGe channel (high-mobility hole) — research-stage, IMEC + Samsung.
  • Ge channel — research, IMEC.
  • III-V channel (InGaAs NMOS) — research, abandoned at major foundries due to integration complexity.
  • 2D materials (MoS2, WS2, WSe2) — IMEC + TSMC + Samsung 2D consortia; potential beyond Si at <1 nm equivalent gate length.

Advanced packaging materials

Bumping and microbumps

C4 (controlled-collapse chip connection) solder bumps — 100-200 µm pitch on flip-chip dice. Sn-Ag-Cu (SAC305: 96.5/3/0.5) or Sn-Cu (lead-free). Underfill: capillary-flow epoxy with silica filler (Hitachi Chemical, Henkel Loctite, Namics).

Cu pillars + microbumps (sub-50 µm pitch) — electroplated Cu pillar with Sn or SnAg cap; thermocompression bonding. Used in 2.5D + 3D advanced packaging.

HBM (high-bandwidth memory) stacks

3D DRAM stacks (HBM2/2E/3/3E/4 generations) with through-silicon vias (TSV). 4-Hi, 8-Hi, 12-Hi, 16-Hi (HBM4) configurations. SK hynix dominant supplier (NVIDIA H100/B100/B200 capacity), Samsung, Micron.

TSV process: deep reactive ion etch (Bosch process variant), Cu electroplating fill, CMP planarization. ~10:1 to 20:1 aspect ratio at 5-10 µm diameter.

2.5D interposer (CoWoS, EMIB, SoIC)

  • TSMC CoWoS (chip-on-wafer-on-substrate) — silicon interposer 60-100 µm thick with TSV + microbumps connecting logic die + HBM stacks; mounted on organic substrate. CoWoS-S (silicon interposer), CoWoS-R (RDL fan-out), CoWoS-L (local silicon bridge — like Intel EMIB). NVIDIA H100/H200/B100/B200, AMD MI300, Google TPU all use CoWoS. Demand 2023-2025 exceeds TSMC capacity; major capacity expansion at AP6/AP7 fabs.
  • Intel EMIB (embedded multi-die interconnect bridge) — silicon bridge embedded in organic substrate; cheaper than full interposer for limited die-to-die regions. Used in Intel Ponte Vecchio GPU, Sapphire Rapids HBM SKUs, Meteor Lake/Arrow Lake/Lunar Lake client chips.
  • Intel Foveros — vertical 3D die stacking (face-to-face); Lakefield Atom (2020), Meteor Lake (2023), Lunar Lake (2024).
  • TSMC SoIC (System on Integrated Chips) — wafer-level 3D bonding with hybrid Cu-Cu bonding at <10 µm pitch. AMD 3D V-Cache (Ryzen 5000X3D/7000X3D/9000X3D series, EPYC Milan-X) since 2022. Apple M1 Ultra UltraFusion (2022).
  • Samsung X-Cube — 3D stacking with TSV; SAINT-S, SAINT-D, SAINT-L for SRAM/HBM/logic stacking.

Organic substrates (laminate)

  • BT (bismaleimide-triazine) laminates — historical mid-range package substrate. Hitachi Chemical, Mitsubishi Gas Chemical.
  • ABF (Ajinomoto Build-up Film, GX-13, GX-92) — buildup dielectric for high-density flip-chip substrates. Ajinomoto Fine-Techno is the sole supplier of ABF film; demand exceeds supply 2022-2025 driving allocation among Ibiden, Unimicron, AT&S, SEMCO substrate manufacturers. ABF shortage was a meaningful 2022-2023 bottleneck for high-end CPUs/GPUs.
  • Substrate manufacturers: Ibiden (Japan; major Intel/AMD supplier), Unimicron (Taiwan; AMD/Apple), AT&S (Austria; Intel + AMD; Kulim Malaysia ramping 2024), Shinko Electric (Japan; Intel), Samsung Electro-Mechanics (Korea), Kinsus + Nanya PCB (Taiwan; lower-end). All running close to capacity.

Glass core substrates

Roadmap announcement 2023-2024: Intel + Samsung + SKC + LG Innotek + Absolics (SKC subsidiary). Glass cores replace organic FR4 core with low-CTE thermally stable glass (Asahi AGC, Corning, Schott) — enables larger substrates (>100 mm reticle field), tighter pitch RDL on top + bottom, integrated passives, photonic integration. Production targeted 2026-2030.

RDL fan-out

  • TSMC InFO (integrated fan-out) — wafer-level fan-out package with RDL on molded encapsulant. Apple iPhone A-series application processors since A10 (iPhone 7, 2016) — Apple’s exclusive package since.
  • LSI ASE SWIFT, FOWLP — generic fan-out wafer-level package, used by mid-range mobile + IoT.
  • ASE Group + Amkor + SPIL + JCET + Powertech — major OSATs (outsourced semiconductor assembly + test).

Hybrid bonding (Cu-Cu direct bonding)

Sub-10 µm pitch interconnect by direct copper-to-copper diffusion bonding at ~400 °C without solder. Used in TSMC SoIC + Sony image sensor stacking (Sony IMX series pixel-on-logic stacking since 2017) + AMD V-Cache.

Equipment: Applied Materials EVG GeminiFB, BESI Datacon hybrid bonder, Tokyo Electron Bonded Wafer (BW) tools.

Die-attach + underfill

  • Sintered silver paste — low-T pressureless or low-pressure sintering at 200-280 °C; superior thermal conductivity ~250 W/m·K (vs Sn-based solder ~60 W/m·K). Critical for SiC + GaN power devices. Suppliers: Heraeus mAgic, Indium Corporation, Henkel Loctite Ablestik, Alpha (MacDermid).
  • Sintered copper — emerging cost-down alternative.
  • Capillary underfill — Henkel Loctite, Namics, Hitachi Chemical (now Resonac).
  • Non-conductive paste (NCP/NCF) — pre-applied underfill films for thermo-compression bonding.

Wire bonding

Au wire (legacy high-reliability, ~$70/oz raw material cost), Cu wire (cost-down since 2010, ~95% of automotive + consumer), Pd-coated Cu (PCC, improved oxidation + reliability — Heraeus PalladioBond, Tanaka). 25-50 µm wire diameter typical; ball + wedge bonds.

MEMS materials

Bulk-micromachining + Bosch DRIE

DRIE (deep reactive ion etch) — Bosch process (patent DE 4241045 1992 — Franz Lärmer, Andrea Schilp Robert Bosch GmbH): alternating SF6 etch + C4F8 passivation pulses produce vertical sidewalls in Si at >50:1 aspect ratio. Used for MEMS resonators, accelerometers, gyroscopes, microphones, BAW filters.

Tools: Plasma-Therm DSE, Oxford Instruments Cobra, SPTS Pegasus, Lam Research Versys, ULVAC.

Sacrificial layers

  • SiO2 sacrificial — released by HF or vapor HF (XACTIX, SPTS Primaxx).
  • Phosphosilicate glass (PSG) — released by HF.
  • Polysilicon sacrificial — released by XeF2.
  • Photoresist sacrificial — released by O2 plasma + solvent.

Piezoelectric materials for MEMS

  • AlN (aluminum nitride) — sputtered film, CMOS-compatible. Bulk Acoustic Wave (BAW) RF filters (Avago/Broadcom, Qorvo, Murata). RF filter market ~$10B/yr.
  • ScAlN (scandium-aluminum nitride) — Sc-substituted AlN, 2-3× higher piezoelectric coefficient than pure AlN. Production at 5G+ filter generation 2020-onward.
  • PZT (lead zirconate titanate, Pb(Zr,Ti)O3) — high d33; used in piezoelectric MEMS actuators, ink-jet print heads (Epson, Brother), ultrasonic transducers (PMUTs). Suppliers: TDK, Murata, Noliac (CTS), APC International, PI Ceramic.
  • LiNbO3, LiTaO3 — single-crystal lithium niobate / tantalate substrates for surface acoustic wave (SAW) filters. Soitec POI (piezoelectric-on-insulator, “PoxiumLN” — Soitec engineered substrate combining thin LiNbO3 on insulating handle, launched 2021). SAW filter suppliers: Murata, Qorvo, Skyworks, Taiyo Yuden.

Silicon-glass bonding

Anodic bonding (Si + borosilicate glass at 300-400 °C with 500-1000 V applied) — hermetic sealing of MEMS chambers. SUSS MicroTec, EVG, AML, Logitech wafer bonders.

SOI MEMS

SOI wafers (typically 10-150 µm device layer on 1-3 µm BOX) enable DRIE-defined vertical structures with built-in etch stop. Sandia SUMMiT, ST AMS, InvenSense (TDK) IMU, Bosch Sensortec accelerometer + gyro.

Emerging memory materials

Mainstream memory: DRAM (1T1C, capacitor + access transistor), 3D NAND (charge-trap floating-gate, 232+ layers at SK hynix/Samsung/Micron 2024), NOR flash, SRAM (6T). Emerging non-volatile memories address persistence + endurance + speed bridging RAM-storage gap.

FeRAM (ferroelectric RAM)

Original PZT-based FeRAM (Ramtron, Fujitsu, Texas Instruments) — capacitor with PZT or SBT ferroelectric; non-volatile by polarization. Niche due to scaling limits (PZT not CMOS-friendly).

Ferroelectric HfO2 (HfZrOx, doped Hf-oxide) — Boescke + Mueller (Qimonda/Nemetics 2011) discovered ferroelectricity in thin HfO2 films, enabling CMOS-compatible ferroelectric memory. FeFET (ferroelectric FET) with HfZrOx gate dielectric — research at GlobalFoundries 22FDX (FMC, Ferroelectric Memory Company), Intel, Sony.

MRAM (magnetic RAM)

Magnetic tunnel junction (MTJ): two ferromagnetic layers separated by tunnel barrier (MgO). Bit stored as parallel/antiparallel magnetization alignment.

  • Toggle MRAM — early 2000s, Freescale 2006 commercial.
  • STT-MRAM (spin-transfer torque) — current-driven switching; mainstream 2010-2024. Everspin Technologies (Chandler AZ, founded 2008 Motorola spinout) commercial since 2014. Samsung embedded STT-MRAM at 28FDS / 14LPP. GlobalFoundries 22FDX eMRAM (embedded MRAM) — first foundry eMRAM 2019; Avalanche Technology, Spin Memory, Numem all competing.
  • SOT-MRAM (spin-orbit torque) — separate read/write paths; faster + more durable; research-stage at IMEC, Samsung.
  • Voltage-controlled MRAM (VCMA) — research; lower energy.

RRAM (resistive RAM, ReRAM)

Filamentary or interface-type switching in metal-oxide stacks (HfO2, TaOx, TiO2). Conductive filament forms/dissolves with applied voltage; resistance state stores bit.

  • Crossbar (Santa Clara CA, founded 2010 by Wei Lu) — Ag/SiOx filament; embedded in MCUs.
  • Weebit Nano (Tel Aviv) — SiOx RRAM in foundry process (SkyWater, GlobalFoundries 22FDX).
  • Adesto (acquired Dialog 2020, now Renesas) — CBRAM (conductive bridge RAM).
  • 4DS Memory (Sydney) — interface-switching ReRAM.

PCM (phase-change memory)

Chalcogenide alloys (GeSbTe, GST) switched between amorphous (high R) and crystalline (low R) by Joule heating. Intel Optane (3D XPoint, co-developed with Micron 2015) was the commercial flagship — Optane DC Persistent Memory + Optane SSD. Intel discontinued Optane 2022 (closed manufacturing 2025) due to weak adoption + Micron exit. Embedded PCM (eFlash replacement) continues at STMicroelectronics + IBM research.

Neuromorphic + memristive

  • Knowm (Santa Fe NM) — memristor-based neuromorphic chips for in-memory ML inference.
  • IBM TrueNorth (2014), IBM NorthPole (2023) — digital neuromorphic.
  • Intel Loihi 2 (2021) — research neuromorphic.
  • BrainChip Akida — commercial neuromorphic SoC.

CXL persistent memory

Compute Express Link expansion modules combining DRAM + persistent backing — Samsung CMM-D, SK hynix Niagara, Micron CXL controllers. Software-defined PMEM after Optane discontinuation.

Major equipment + materials suppliers

Lithography

  • ASML (Veldhoven NL) — sole EUV supplier; ArF immersion dominant. TWINSCAN NXE:3400/3600/3800 (standard EUV NA 0.33), NXE:5000 (high-NA 0.55, first system shipped to Intel December 2023, TSMC + Samsung 2024-2025).
  • Canon Tokki — i-line + KrF + some specialty ArF.
  • Nikon — ArFi (declining share), specialty + back-end packaging litho.

Deposition + etch

  • Applied Materials (Santa Clara CA) — broadest portfolio: Endura PVD, Producer CVD, Olympia ALD, Centura epi, Sym3 etch, Reflexion CMP, Black Diamond low-k, Selectra selective etch. Market leader by revenue.
  • Lam Research (Fremont CA) — etch leader (Versys, Kiyo, Flex), deposition (SABRE Cu electroplating, ALTUS W ALD, VECTOR PECVD). Cu electrofill dominance + dielectric etch.
  • ASM International / ASMI (Almere NL) — ALD pioneer; Pulsar (Hf-oxide HKMG), Eagle XP8, Polygon batch ALD.
  • Tokyo Electron / TEL (Tokyo) — coater/developer (Clean Track for ASML scanners), ALD (Trias), etch (Vigus, Tactras), batch CVD (Triase+).
  • Kokusai Electric (acquired Applied Materials 2023, pending close 2024-2025) — batch furnace + ALD; spinoff from Hitachi Kokusai.
  • Hitachi High-Tech — etch (M-712E magnetic-field-assisted MERIE), e-beam.
  • ASMPT, EVG, SUSS MicroTec, AMEC (Advanced Micro-Fabrication Equipment China) — back-end + China alternatives.

Metrology + inspection

  • KLA Corporation (Milpitas CA) — overlay, defect inspection (29xx series), CD metrology (eDR), wafer inspection (Surfscan). ~50% of front-end metrology market.
  • Hitachi High-Tech — CD-SEM, e-beam inspection.
  • Onto Innovation (post Rudolph-Nanometrics merger 2019) — overlay, lithography metrology.
  • Camtek — wafer-level + advanced-packaging inspection.
  • Park Systems — atomic force microscopy.
  • Bruker — XRD, XRF, fluorescence-based metrology.

Wafers

  • Shin-Etsu Handotai (Tokyo) — world leader, ~30% Si wafer market.
  • SUMCO (Tokyo) — ~25%.
  • GlobalWafers (Hsinchu Taiwan) — post-Siltronic acquisition attempt blocked 2022 by German FCO; remains independent. ~15-20%.
  • Siltronic (Munich) — ~10-15%.
  • SK Siltron (Korea) — ~5%.
  • Soitec (Bernin France) — SOI dominant + GaN-on-Si + InP-on-Si engineered substrates.

Photoresists + materials

  • JSR Corporation (post-2024 buyout) — broad portfolio.
  • Tokyo Ohka Kogyo (TOK).
  • Shin-Etsu Chemical.
  • Sumitomo Chemical.
  • Dongjin Semichem (Korea — supplied Samsung; Japan-Korea 2019 export controls highlighted strategic dependence).
  • Fujifilm Electronic Materials.
  • DuPont Electronic Materials, Versum/Merck KGaA (post-2019 Merck-Versum merger).

Substrates + packaging

  • Ibiden, Unimicron, AT&S, Shinko Electric, Samsung Electro-Mechanics, Kinsus, Nanya PCB — ABF substrate manufacturers.
  • Ajinomoto — sole ABF film source.
  • ASE Group (Sun Moon Lake Taiwan), Amkor, JCET, SPIL, Powertech, ChipMOS — OSATs.

Specialty chemicals + slurries

  • CMC Materials (Entegris subsidiary post-2022 acquisition).
  • DuPont Electronics & Industrial.
  • Versum/Merck KGaA.
  • Fujimi.
  • Cabot Microelectronics (renamed CMC).
  • KCTech (Korea).
  • Henkel, Showa Denko/Resonac, Linde, Air Liquide, Air Products.

Case studies and recent program highlights (2023-2026)

TSMC N3 + N2 ramp

N3E (3 nm enhanced FinFET-like, 2023): Apple A17 Pro (iPhone 15 Pro Sep 2023), M3 (Oct 2023), M4 (May 2024). N3B (original 3 nm, low yield): A17 Pro only. N3P (2024-2025 refinement, used at AMD MI350 family + Apple A18 Pro). N3X (high-performance, 2025).

N2 (2 nm GAA nanosheet) — risk production 2H2024, volume 2025. Apple + AMD first customers. Backside power delivery deferred to N2P (2026).

Intel 18A (1.8 nm-class) + 20A

Intel 20A (Arrow Lake — cancelled for desktop 2024, moved to 18A; some mobile use). Intel 18A — RibbonFET nanosheet + PowerVia backside power delivery; Panther Lake mobile launch Q4 2025; Clearwater Forest server 2026. Intel claims process leadership re-establishment at 18A.

Samsung SF3 + SF2

SF3 (3 nm GAA, 2022 first production) — Samsung Galaxy + cryptocurrency mining chips. Yield issues in 2022-2023; SF3P (refined) better. SF2 (2 nm GAA, 2025 production targeted). SF2P (2 nm with BSPDN, 2026).

CoWoS demand explosion

NVIDIA H100 (Hopper, 2022) + H200 + B100/B200 (Blackwell, 2024-2025) AI GPUs all require CoWoS-S/L. TSMC CoWoS capacity ramping from ~15 k wafers/month (2023) → 35 k (2024) → 55 k+ (2025). Constraint on AI compute supply.

HBM4 + 12-Hi/16-Hi stacks

SK hynix 12-Hi HBM3E (36 GB per stack) qualified for NVIDIA Blackwell (2024). HBM4 spec (2025-2026) — 16-Hi stacks, 2048-bit interface (vs HBM3 1024-bit), 1.5 TB/s bandwidth per stack. Bonded hybrid Cu-Cu bonding emerging at HBM4.

ABF substrate shortage

2022-2024 — Ajinomoto ABF allocation among Ibiden + Unimicron + AT&S forced AMD + Intel to ration substrate-constrained SKUs. Substrate-makers capex >$10B 2023-2026 to expand capacity. Eased somewhat 2025 as PC demand softened.

SiC 200 mm transition

Wolfspeed Mohawk Valley NY 200 mm SiC fab — first commercial 200 mm SiC production. Ramp slower than originally planned (Cree → Wolfspeed financial pressures 2023-2025). ST Catania Italy, Onsemi Czech, Coherent 200 mm capacity expansions in parallel. Soitec SmartSiC engineered substrate licensed by ST + ramp on 200 mm.

GaN-on-Si acquisitions

Infineon acquired GaN Systems (Sep 2023, $830M) — consolidating GaN power discrete supply. Renesas + Transphorm partnership. Navitas IPO + commercial ramp continued. EPC + Innoscience competing on consumer fast-charger + datacenter PSU sockets.

IBM 2 nm test chip + research

IBM Research May 2021 — 2 nm test chip with 3-stack nanosheet GAA. Demonstrated 50 B transistors at fingernail-area chip; never went to volume production (IBM no longer fabricates leading-edge), but technology licensed to TSMC + Samsung + Intel via consortium agreements.

High-NA EUV shipment

ASML NXE:5000 high-NA (NA 0.55) EUV shipped to Intel December 2023 — first installation at Hillsboro D1X. TSMC + Samsung systems 2024-2025. Production use targeted Intel 14A node (post-18A) and TSMC A14 (post-N2).

EUV mask blank + pellicle constraints

ASML rate-limited by EUV mask blank supply (HOYA + AGC) + pellicle scaling for high-NA. Photoresist dose constraints persist — JSR Inpria MOR helps but slows throughput. Dose-budget management is a meaningful production-economics lever at 3 nm + 2 nm.

CHIPS Act + EU Chips Act funding (2022-2026)

US CHIPS and Science Act (\52$24$66$ B award March 2024), Samsung Texas, Micron NY, GlobalFoundries NY. EU Chips Act EUR 43 B — TSMC Dresden (with Bosch + Infineon + NXP), Intel Magdeburg (delayed Sep 2024), STMicro Crolles. Japan METI subsidies for TSMC Kumamoto, Rapidus Hokkaido (2 nm with IBM tech, 2027 production target).

Further reading

  • Wolf, S — Silicon Processing for the VLSI Era, Volumes 1-4, Lattice Press. Comprehensive multi-volume reference.
  • Plummer, J D + Deal, M D + Griffin, P B — Silicon VLSI Technology, Prentice Hall 2000.
  • Quirk, M + Serda, J — Semiconductor Manufacturing Technology, Prentice Hall 2001. Process-engineering-oriented.
  • Lapedus, M (Semiconductor Engineering, semiengineering.com) — industry coverage of process + materials.
  • Sze, S M + Lee, M K — Semiconductor Devices: Physics and Technology, 3rd ed., Wiley 2012.
  • George, S M — “Atomic Layer Deposition: An Overview,” Chem Rev 2010, 110:111.
  • Mack, C — Fundamental Principles of Optical Lithography, Wiley 2007.
  • Bakshi, V (ed) — EUV Lithography, 2nd ed., SPIE Press 2018.
  • IRDS (International Roadmap for Devices and Systems), annual editions — successor to ITRS roadmap.
  • Heterogeneous Integration Roadmap (IEEE), annual.

Adjacent

Graph View