Circuit Analysis (DC Fundamentals) — Engineering Reference

Circuit Analysis (DC Fundamentals)

1. At a glance

Circuit analysis is the procedure for determining every voltage, current, and instantaneous power in a network of interconnected sources and passive elements (resistors R, inductors L, capacitors C, plus active sources). It is the load-bearing foundation underneath nearly all of electrical and electronics engineering: power distribution, signal conditioning, sensor interfacing, motor drives, transmission lines, integrated-circuit design, and embedded firmware that has to reason about analog inputs all rest on it.

DC analysis is the limit case in which all sources are constant and all transients have died out. In that steady state, inductors look like short circuits (zero volts across, any current through) and capacitors look like open circuits (any voltage across, zero current through). The network reduces to a linear resistive problem governed by Ohm’s law and Kirchhoff’s two conservation laws. AC steady-state analysis — phasors, complex impedance, frequency response — extends the same machinery to sinusoidal sources and is treated in the sister note [[Engineering/ac-analysis-three-phase]].

A practising engineer reaches for circuit analysis several times an hour: sizing a current-limiting resistor for an LED, picking a voltage-divider ratio for an ADC input, estimating IR drop in a power rail, debugging why a transistor stage has the wrong bias point, or sanity-checking a SPICE simulation result before trusting it. The toolset is small (KCL, KVL, Ohm, Thevenin, Norton, mesh, nodal, superposition), but fluency with it is the difference between an engineer who can read a schematic and one who can only build from a recipe.

2. First principles

Charge and current. Charge q is measured in coulombs (C). Current is the time rate of charge flow through a surface:

• i = dq/dt, units amperes (A) = C/s.
• Conventional current flows from + to − externally (opposite to electron flow). The sign convention matters; reversing arrow direction reverses the sign of i.

Voltage. Voltage v between two points is the energy per unit charge required to move a test charge between them:

• v = dw/dq, units volts (V) = J/C.

Power. Instantaneous power delivered to a two-terminal element under the passive sign convention (current entering the + terminal):

• p = v·i, units watts (W) = J/s.
• p > 0 means the element absorbs energy; p < 0 means it delivers energy.

Energy. w = ∫p dt, units joules (J) = W·s. Practical billing unit is the kilowatt-hour (1 kW·h = 3.6 MJ).

Passive elements.

• Resistor: v = i·R, with R in ohms (Ω = V/A). Energy is dissipated as heat: p = v²/R = i²R.
• Inductor: v = L·di/dt, with L in henries (H = V·s/A). Stores energy in magnetic field: w = ½L·i².
• Capacitor: i = C·dv/dt, with C in farads (F = A·s/V). Stores energy in electric field: w = ½C·v².

DC steady state. With di/dt = 0 and dv/dt = 0:

• Inductor: v = L·0 = 0 → acts as a short circuit (wire).
• Capacitor: i = C·0 = 0 → acts as an open circuit (gap). This collapse is what makes DC analysis a purely resistive problem.

Kirchhoff’s Current Law (KCL). The algebraic sum of currents entering any node (or any closed surface enclosing part of a circuit) equals zero:

• Σ i_into_node = 0. This is conservation of charge — charge does not pile up at a node.

Kirchhoff’s Voltage Law (KVL). The algebraic sum of voltages around any closed loop equals zero:

• Σ v_around_loop = 0. This is conservation of energy — a charge taken around a loop and returned to its starting point gains and loses equal amounts of energy.

Source types.

• Independent voltage source — enforces v(t) regardless of i. An ideal source has zero internal resistance.
• Independent current source — enforces i(t) regardless of v. An ideal source has infinite internal resistance.
• Dependent (controlled) sources — output is a function of some other circuit variable. Four kinds: VCVS (voltage-controlled voltage source), VCCS (voltage-controlled current source), CCVS (current-controlled voltage source), CCCS (current-controlled current source). These are the bookkeeping device that makes transistors, op-amps, and amplifiers tractable inside the linear framework.

Linearity. A circuit is linear if every element’s v–i relation is linear (resistors, ideal sources, dependent sources whose coefficient is constant). Linearity is what enables superposition, Thevenin/Norton equivalence, and the matrix formulation of mesh and nodal analysis. Diodes, BJTs, MOSFETs, and saturating inductors are not linear; they must be linearised about an operating point (small-signal model) before linear network theorems apply.

3. Practical math / design equations

Series and parallel reduction

Series resistance (same current through each element):

R_total = R₁ + R₂ + … + R_n

Parallel resistance (same voltage across each element):

1/R_total = 1/R₁ + 1/R₂ + … + 1/R_n

For exactly two resistors in parallel the “product over sum” form is faster:

R_total = R₁ · R₂ / (R₁ + R₂)

Capacitors and inductors invert the rules:

• Capacitors in parallel add (C_total = ΣC_i); in series combine like resistors in parallel.
• Inductors in series add (L_total = ΣL_i); in parallel combine like resistors in parallel.

Voltage and current dividers

Voltage divider — a series chain of R₁ and R₂ across v_in, output taken across R₂:

v_out = v_in · R₂ / (R₁ + R₂)

Valid only when the load drawing current from v_out is negligible compared to the divider current (rule of thumb: load impedance ≥ 10× R₂).

Current divider — two resistors in parallel carrying a total current i_total. The current through R₁ is:

i_R1 = i_total · R₂ / (R₁ + R₂)

The bigger resistor steers less current — the opposite of the voltage divider’s bigger-gets-more relationship. This sometimes catches students.

Mesh analysis

Mesh analysis writes KVL around each independent loop (mesh) of a planar circuit. Procedure:

1. Identify the meshes (the “windowpanes” of the planar drawing). A circuit with n nodes and b branches has b − n + 1 meshes.
2. Assign a mesh current — by convention clockwise — to each mesh.
3. For each mesh write KVL: voltage rises = voltage drops. The current through any branch shared between two meshes is the difference of the two mesh currents.
4. Solve the resulting linear system.

Mesh is most natural when the circuit has many nodes but few loops, and when the sources are predominantly voltage sources. Current sources require a supermesh (combine the two adjacent meshes into one super-loop and add the constraint that their mesh-current difference equals the source value).

Nodal analysis

Nodal analysis writes KCL at each non-reference node. Procedure:

1. Pick one node as the reference (ground, v = 0).
2. Assign a node voltage v_k to each remaining node.
3. For each non-reference node write KCL with currents expressed as (v_a − v_b)/R using Ohm’s law.
4. Solve.

Nodal is generally preferred when the circuit has more loops than nodes, and when sources are predominantly current sources. Voltage sources connecting two non-reference nodes force a supernode: combine the two nodes’ KCL equations into one and add the constraint v_a − v_b = V_source.

In matrix form nodal analysis becomes G·v = i, where G is the conductance matrix (symmetric for circuits with no controlled sources), v is the vector of node voltages, and i is the vector of source currents injected at each node. This is the formulation SPICE uses internally.

Thevenin’s and Norton’s theorems

Thevenin: any linear two-terminal network is equivalent, from the perspective of an external load, to a single voltage source V_th in series with a single resistance R_th.

Norton: dually, equivalent to a single current source I_N in parallel with a single resistance R_N.

Equivalence relations:

• V_th = I_N · R_N
• R_th = R_N
• Source transformation works both ways and is a useful intermediate simplification step.

To find the Thevenin equivalent of a network at terminals A–B:

1. V_th = open-circuit voltage v_AB with the load removed.
2. R_th = ratio of open-circuit voltage to short-circuit current: R_th = V_oc / I_sc.
3. Alternative for R_th when no dependent sources are present: zero out every independent source (voltage source → short, current source → open) and compute the resistance seen from A–B by inspection (series/parallel reduction). With dependent sources you must use V_oc / I_sc, or apply a test source.

Superposition

For a linear circuit driven by multiple independent sources, the response at any point is the algebraic sum of the responses to each source acting alone (all others zeroed: V-sources shorted, I-sources opened). Dependent sources stay in place — never zero them. Superposition is conceptually clean but algebraically expensive; it is most useful when one source dominates and you want to estimate the perturbation from the others, or when isolating noise contributions in analog design.

Maximum power transfer

A Thevenin source (V_th, R_th) delivers maximum power to a resistive load when:

R_L = R_th

and the resulting power is:

P_max = V_th² / (4·R_th)

This is the right design choice for signal transfer (RF antennas, communication links). It is the wrong design choice for power delivery, where high efficiency is the goal: efficiency at matched load is only 50%. Power-system designers operate with R_L ≫ R_th to keep efficiency near unity and accept reduced absolute power transfer.

Worked example 1 — Wheatstone bridge Thevenin equivalent

A Wheatstone bridge has a 10 V battery driving two parallel branches. Top branch: R₁ = 1.0 kΩ in series with R₂ = 2.0 kΩ. Bottom branch: R₃ = 1.5 kΩ in series with R₄ = 3.0 kΩ. Galvanometer terminals are the midpoint A of the top branch and the midpoint B of the bottom branch. Find the Thevenin equivalent across A–B.

V_th (open-circuit voltage):

• v_A = 10 V · R₂/(R₁+R₂) = 10 V · 2.0/3.0 = 6.667 V.
• v_B = 10 V · R₄/(R₃+R₄) = 10 V · 3.0/4.5 = 6.667 V.
• V_th = v_A − v_B = 0 V.

The bridge is balanced (R₁/R₂ = R₃/R₄ = 1/2), so no galvanometer current flows regardless of galvanometer resistance — the classic null-detection result used in precision sensor measurement.

R_th: zero the 10 V source (replace with a wire). From A–B one sees R₁ ∥ R₂ on one side (1.0 ∥ 2.0 = 0.667 kΩ) in series with R₃ ∥ R₄ on the other (1.5 ∥ 3.0 = 1.0 kΩ).

• R_th = 0.667 kΩ + 1.0 kΩ = 1.667 kΩ.

So the equivalent is 0 V in series with 1.667 kΩ. If R₂ drifts up to 2.05 kΩ (1 % sensor change), V_th becomes 10·(2.05/3.05) − 6.667 = 0.054 V — about 54 mV, which an instrumentation amplifier can resolve trivially.

Worked example 2 — IR drop in a battery feeder

A 12.0 V lead-acid battery feeds a 100 W incandescent bulb (rated at 12 V) through 5.0 m of 16 AWG copper wire to a switch panel and 5.0 m back — 10 m round trip. 16 AWG copper has a DC resistance of about 13.2 mΩ/m at 20 °C, so the round-trip wire resistance is:

R_wire = 10 m · 13.2 mΩ/m = 132 mΩ = 0.132 Ω.

The bulb at rated voltage draws I_rated = 100 W / 12 V = 8.33 A and presents a hot-filament resistance R_bulb = V²/P = (12 V)²/100 W = 1.44 Ω.

In the actual circuit the bulb sees a Thevenin source of 12.0 V with R_th = 0.132 Ω (assuming an ideal battery for simplicity). The loop current is:

I = 12.0 V / (0.132 Ω + 1.44 Ω) = 12.0 V / 1.572 Ω = 7.633 A.

Voltage at the bulb terminals:

V_bulb = I · R_bulb = 7.633 A · 1.44 Ω = 10.99 V.

Wire dissipation:

P_wire = I² · R_wire = (7.633 A)² · 0.132 Ω = 7.69 W.

The bulb actually receives:

P_bulb_actual = I² · R_bulb = (7.633 A)² · 1.44 Ω = 83.9 W.

So the 8 % voltage drop across the wires costs about 16 % of the bulb’s rated brightness (incandescent luminous output goes roughly as V^3.4). 7.69 W spread over 10 m of wire is about 0.77 W/m, well within the thermal capacity of 16 AWG insulation — but a designer who wanted full bulb brightness would upgrade to 12 AWG (about 5.2 mΩ/m, cutting wire drop to ~0.4 V) or reduce the run length.

Worked example 3 — Voltage divider for 3.3 V from 5 V with a 1 mA load

Goal: produce 3.3 V from a 5.0 V rail to feed a sensor that draws 1.0 mA, using a resistive divider only.

The unloaded divider ratio is 3.3/5.0 = 0.66, so R₂/(R₁+R₂) = 0.66 → R₁ = 0.515·R₂.

The bleed current i_bleed through R₁ and R₂ in the no-load case is 5 V / (R₁+R₂). To keep the output stiff against the 1 mA load, set i_bleed ≥ 10·i_load = 10 mA. Then:

• R₁ + R₂ = 5.0 V / 10 mA = 500 Ω.
• R₂ = 500 / 1.515 = 330 Ω; R₁ = 500 − 330 = 170 Ω.

Pick standard E24 values: R₁ = 180 Ω, R₂ = 330 Ω (closest pair). Recompute:

• Unloaded v_out = 5.0 · 330/(180+330) = 5.0 · 0.647 = 3.235 V.
• With 1 mA load, Thevenin equivalent of the divider is V_th = 3.235 V, R_th = 180 ∥ 330 = 116.5 Ω. Loaded output = 3.235 − 1 mA · 116.5 Ω = 3.235 − 0.117 = 3.118 V.

That is ~5.5 % below target and load-dependent — illustrating why a resistive divider is almost never the right way to power a sensor. The bleed current also wastes 5 V · 10 mA = 50 mW continuously, which dominates the 3.3 mW sensor consumption. The right answer is an LDO (e.g. AP2112-3.3) or a reference IC (e.g. LM4040-3.3), reserving the divider topology for ADC scaling and biasing where the downstream impedance is genuinely high.

4. Reference data

Standard resistor E-series

The IEC 60063 preferred-number series provide log-spaced values that round-trip well across decades. Pick the tightest series your tolerance allows.

Series	Tolerance	Values per decade	Decade pattern (starts at 1.0)
E12	±10 %	12	1.0, 1.2, 1.5, 1.8, 2.2, 2.7, 3.3, 3.9, 4.7, 5.6, 6.8, 8.2
E24	±5 %	24	1.0, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 2.0, 2.2, 2.4, 2.7, 3.0, 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1
E48	±2 %	48	(three-digit values, e.g. 1.00, 1.05, 1.10, 1.15 …)
E96	±1 %	96	(three-digit values, e.g. 1.00, 1.02, 1.05 … 9.76)
E192	±0.5 %	192	(three-digit, finest commonly stocked)

A “330 Ω, 5 %” resistor means an E24 value with ±5 % tolerance; “33.2 kΩ, 1 %” is E96.

Resistor power ratings

Package / rating	Typical use
0402 SMD, ~1/16 W (62.5 mW)	RF, high-density logic.
0603 SMD, ~1/10 W (100 mW)	General-purpose digital signal.
0805 SMD, ~1/8 W (125 mW)	Default for hand-soldered SMD.
1206 SMD, ~1/4 W (250 mW)	Pull-ups on noisier rails, gate resistors.
Through-hole 1/4 W	Default through-hole resistor.
Through-hole 1/2 W, 1 W	Power dividers, snubbers, current limiters.
Through-hole 2 W, 5 W	Inrush limiters, dummy loads.
Wirewound 10–100 W (chassis-mount)	Bleed loads, brake resistors.
Aluminium-clad 100–1000 W	Motor brake resistors, dump loads.

Derate to 50–60 % of rated power for long-term reliability and to keep the surface below ~90 °C in a typical enclosure.

Wire gauges and ampacity (copper, 60 °C insulation, free air)

AWG	mm² (approx)	DC resistance (mΩ/m @ 20 °C)	Typical ampacity
30	0.05	339	0.5 A
24	0.20	84.2	2 A
22	0.33	53.0	3 A
20	0.52	33.3	5 A
18	0.82	20.9	7 A
16	1.31	13.2	10 A
14	2.08	8.29	15 A
12	3.31	5.21	20 A
10	5.26	3.28	30 A
8	8.37	2.06	50 A
6	13.3	1.30	65 A
4	21.2	0.815	85 A
2	33.6	0.513	115 A
1/0	53.5	0.323	150 A
4/0	107	0.161	230 A

These are rules of thumb, not code. For installation in conduit, in cable bundles, or at elevated temperature, derate per NEC Table 310.16 (US) or IEC 60364-5-52 (most other countries). Wire resistance has a positive temperature coefficient of about +0.39 %/°C for copper; multiply by 1.20 at 70 °C, 1.40 at 120 °C.

Capacitor families and typical value ranges

Family	Value range	Voltage	Notes
Ceramic C0G/NP0	1 pF – 100 nF	10 V – 1 kV	Most stable; <1 % drift over temp/V; precision RF/timing.
Ceramic X7R	100 pF – 10 µF	6.3 V – 100 V	Workhorse decoupling; ±15 % over −55 to +125 °C; loses up to 80 % capacitance at rated DC bias.
Ceramic Y5V/Z5U	1 nF – 10 µF	6.3 V – 50 V	Avoid for new designs; huge temp/V drift.
Film (polypropylene, polyester)	1 nF – 100 µF	50 V – 2 kV	Low ESR, audio, snubbers, motor-run.
Aluminium electrolytic	1 µF – 100 mF	6.3 V – 600 V	Bulk PSU filtering; polarised; ESR matters; lifetime sensitive to temperature (Arrhenius 2× per −10 °C).
Tantalum	100 nF – 1 mF	4 V – 50 V	Low ESR, small, polarised; fails as a short and can ignite if overvolted. Derate to 50 % of rated V.
Polymer aluminium / polymer tantalum	1 µF – 1 mF	2.5 V – 35 V	Very low ESR, modern bypass; no wet-out failure mode.
Supercapacitor (EDLC)	0.1 F – 3000 F	2.5 V – 5 V	Backup power, energy buffering; not a “capacitor” in the analysis sense (highly nonlinear, large ESR).

5p. Theory

Circuit analysis is the quasi-static, lumped-element limit of Maxwell’s equations. Three approximations make the simplification valid:

1. Lumped-element approximation. Circuit dimensions ≪ shortest signal wavelength. Then displacement-current contributions outside capacitor structures are negligible and one can speak of “the” voltage across an element and “the” current through it (otherwise both quantities vary continuously along the conductor).
2. No magnetic-field interaction outside inductors. All flux is confined to the inductor’s geometry; coupling is captured explicitly via mutual inductance M or transformer models.
3. No charge accumulation outside capacitors. All net charge sits between capacitor plates; conductors and resistors remain electrically neutral on the macroscale.

Under these approximations Maxwell’s curl equations collapse: ∮E·dℓ = 0 around any loop that does not enclose changing flux becomes KVL, and ∇·J = 0 for an ideal conductor becomes KCL at every node. The element constitutive relations (v = iR, v = L di/dt, i = C dv/dt) close the system.

Linear network theorems (superposition, Thevenin, Norton, reciprocity, maximum power transfer, substitution theorem) all follow from a single algebraic fact: the network’s solution is a linear map from the source vector to the response vector. This map can always be represented as a matrix inverse (G⁻¹ for nodal, R for mesh). Superposition is linearity made operational; Thevenin/Norton are statements that any two-port reduction of the linear map has rank ≤ 1 from the load’s perspective.

Tellegen’s theorem. For any network whose currents satisfy KCL and whose voltages satisfy KVL — even if the v–i relations are not the actual element constitutive laws — the sum Σ v_k·i_k over all branches is identically zero. In the special case where v and i belong to the same circuit at the same instant, this is conservation of power: Σp_absorbed = Σp_delivered. Tellegen is more general (the v and i need not even come from the same network — only the same graph), which makes it the deep theoretical foundation underneath conservation arguments.

Substitution theorem. Any branch carrying a known voltage v_b and current i_b can be replaced by an independent v-source of value v_b (or i-source of value i_b) without changing any other voltage or current. This is the licence behind “Thevenin-equivalent the rest of the network.”

Reciprocity. In a linear network containing only resistors and independent sources (no dependent sources), if a v-source V at branch A produces current I at branch B, then placing V at B produces the same I at A. Used in antenna theory and in deriving symmetry properties of impedance matrices.

6p. Application

The day-to-day workflow of practical circuit analysis is more pragmatic than the textbook sequence suggests:

1. Look first for series/parallel reductions. Most real schematics collapse by 50–80 % through inspection alone. Spotting that two paths share both endpoints (parallel) or that a wire carries a single current with no branches (series) is the highest-leverage skill.
2. Replace the part you don’t care about with a Thevenin equivalent. When analysing a load (LED, op-amp, transistor, sensor), don’t try to track every node of the surrounding network — reduce everything else to V_th and R_th seen from the load’s terminals.
3. Voltage / current dividers as first-pass approximations. Even when loaded, they give a baseline that is typically within 10 %. Calculate the unloaded value first; then apply the load-correction once.
4. Mesh or nodal only when reductions exhaust. Bridges, ladder networks with five or more resistors, and anything with two or more independent sources all become tractable once you write the linear system. Modern practice: write it out by hand for circuits up to ~6 unknowns, hand to NumPy/Octave/SymPy for anything larger.
5. Sanity-check with limits. Set a resistor to 0 or ∞ — does the answer go where it should? Set a source to zero — does the rest still solve consistently? KCL at one extra node you didn’t use — does it balance?
6. SPICE for nonlinear or frequency-dependent. Transistors, diodes, op-amps with rails, transformers, transmission lines — beyond the linear-resistive regime, run a simulation. Use hand analysis to set expectations and catch SPICE convergence failures or netlist errors.

A common engineering-judgement call: how loaded is “lightly loaded”? Rule of thumb — load impedance ≥ 10× the Thevenin source impedance keeps the unloaded approximation within 10 % error; 100× keeps it within 1 %. When that is not affordable (battery-powered designs, picoampere photodetectors), explicitly model the loading.

7p. Edge cases & assumptions

Lumped-element breakdown — the λ/10 rule. The lumped approximation requires the circuit’s largest dimension ℓ to be smaller than about 1/10 of the wavelength λ of the highest frequency of interest. With λ = c/f and signal propagation in PCB FR-4 of about 0.6c:

• At 100 MHz, λ ≈ 1.8 m → ℓ ≤ 18 cm; most PCB traces are safe.
• At 1 GHz, λ ≈ 18 cm → ℓ ≤ 1.8 cm; long traces become transmission lines.
• At 10 GHz, λ ≈ 1.8 cm → ℓ ≤ 1.8 mm; even via stubs matter. Above these thresholds you must reach for transmission-line analysis (telegrapher’s equations, S-parameters, Smith chart). See [[Engineering/ac-analysis-three-phase]] for the AC-impedance bridge.

Real components have parasitics.

• Resistor: typical SMD has 1–5 nH of lead inductance and 0.5–2 pF of shunt capacitance. Self-resonant frequency for an 0805 1 kΩ is ~1 GHz; for a wirewound 100 Ω it can be <1 MHz.
• Capacitor: ESL (equivalent series inductance) sets the self-resonant frequency, above which a capacitor behaves inductively. ESR (equivalent series resistance) determines ripple-current heating and decoupling effectiveness. A 10 µF X7R 0805 typically has ESL ≈ 1 nH (SRF ~50 MHz) and ESR ~10 mΩ. A 100 µF aluminium electrolytic typically has ESL ~15 nH and ESR ~100 mΩ.
• Inductor: DCR (DC resistance) of the winding limits efficiency in DC-DC converters; self-capacitance between turns sets the self-resonant frequency above which it looks capacitive; magnetic saturation collapses inductance at high currents.

Real sources have output impedance.

• A 9 V alkaline battery is roughly 9 V with 1–5 Ω internal resistance new; rises to 20+ Ω near end-of-life.
• A bench DC power supply is typically <10 mΩ in constant-voltage mode.
• A signal generator is typically 50 Ω (RF) or 600 Ω (audio).

Temperature coefficient. Resistor tolerances are nominal at 25 °C; standard TC is ±100 ppm/°C for thick-film, ±25 ppm/°C for thin-film, ±5 ppm/°C for precision foil. Capacitor C drifts heavily with temperature (X7R ±15 % over −55 to +125 °C) and DC bias (X7R loses up to 80 % at rated voltage). Never trust a single nominal value in precision design.

Self-heating of resistors. A 1/4 W resistor dissipating 200 mW rises ~80 °C above ambient. At that ΔT a ±100 ppm/°C resistor drifts 0.8 %. For ADC scaling and precision current sensing, use thin-film resistors and keep dissipation below 10 % of rated.

Ground is not ground. Two points labelled “GND” on a schematic can sit at meaningfully different potentials in the physical board if there is current flow between them in a non-zero copper resistance. This is the source of much grief in mixed-signal design (audio, ADC reference, sensor cabling). Star grounding and Kelvin (4-wire) sensing exist because of this.

8p. Tools & software

Schematic capture + simulation suites:

• KiCad — open-source EDA; ngspice-based simulator integrated since 6.0. Good for hobby and small-team production.
• LTspice — free from Analog Devices (originally Linear Technology); fastest convergence on the market for switching converters; weak schematic UI; massive library of vendor parts. The de-facto standard for analog hand-simulation.
• Cadence PSpice / Cadence OrCAD — commercial, dominant in large EDA shops; deep model libraries, expensive seats.
• Altium Designer — commercial commercial suite with integrated SPICE; primary competitor to OrCAD.
• EasyEDA — browser-based, tied to JLCPCB/LCSC supply chain; pleasant for quick prototypes.
• EAGLE — Autodesk’s tool; widely used historically by makers; declining as KiCad matures.

Pure simulators:

• ngspice — open-source SPICE3 derivative, the engine inside KiCad. CLI-driven; reasonable nonlinear convergence.
• Qucs-S / QucsStudio — open-source, GUI-friendly; supports RF and S-parameter analysis.
• Spectre (Cadence) — commercial, the analog/RF simulator of choice in IC design.

Pedagogical / web-based:

• Falstad Circuit Simulator — browser-based, real-time animated; the fastest way to build intuition for transient behaviour.
• CircuitVerse — browser-based, digital-logic-focused.
• Tinkercad Circuits — Autodesk-owned, includes virtual Arduino and breadboard view; aimed at K-12 / introductory.
• Multisim Live — NI’s browser version of Multisim.

Symbolic / programmatic analysis:

• SymPy with the sympy.physics.circuits family — symbolic mesh and nodal analysis; useful for parameter sweeps and exact algebraic answers.
• lcapy (Python) — purpose-built symbolic circuit analysis; emits LaTeX and SPICE both.
• MATLAB Simscape Electrical — graphical, MathWorks-tier polish, expensive.

Bench instruments (the other half of “tools”):

• Digital multimeter (DMM): 6½-digit (Keysight 34465A, Keithley DMM6500) for precision lab; 3½–4½-digit (Fluke 87, UNI-T UT139) for field.
• Oscilloscope: 100 MHz / 1 GS/s entry-tier (Rigol DS1000Z, Siglent SDS1104X-E); 4-channel mixed-signal at 200 MHz–1 GHz for typical embedded debug.
• Bench DC power supply: triple-output 30 V / 5 A units (Rigol DP832, Siglent SPD3303X); linear types for low-noise analog work.
• Electronic load: Itech IT8500, Rigol DL3000 series for testing supplies into realistic loads.
• LCR meter: for component characterisation (ESR, ESL); DE-5000 (hobby), Keysight E4980A (lab).

11. Cross-references

• [[Engineering/ac-analysis-three-phase]] — extends the same machinery to sinusoidal sources via phasors, impedance, and three-phase power systems.
• [[Engineering/semiconductor-devices]] — diode, BJT, MOSFET small-signal models built on Thevenin/Norton equivalents.
• [[Engineering/op-amps]] — virtual-short and virtual-ground simplifications make nodal analysis trivial for op-amp circuits.
• [[Engineering/power-electronics]] — switching converters analysed as piecewise-linear circuits, averaged-model state-space, and small-signal control loops.
• [[Engineering/digital-logic]] — CMOS gates as switched RC networks; propagation delay from RC analysis.
• [[Engineering/electric-motors]] — motors as back-EMF voltage sources behind a series R-L; drive electronics built on these models.
• [[Engineering/pcb-design]] — physical layout introduces parasitic L and C not in textbook analysis; this is where the lumped assumption frays.
• [[Engineering/microcontrollers]] — GPIO drive strength, pull-up sizing, ADC input impedance are everyday circuit-analysis problems.
• [[Engineering/rf-design]] — what to do when the λ/10 rule fails.
• [[Robotics/power-systems]] — battery internal resistance, BMS topologies, motor-controller bus capacitance all draw on this foundation.
• [[Robotics/comm-buses]] — voltage dividers, anti-alias filters, current-shunt amplifiers.
• [[Languages/Tier3/hdl]] — SPICE netlist syntax for capturing and simulating these circuits programmatically.
• [[Languages/Tier3/hdl]] — analog hardware description for behavioural modelling of nonlinear elements.

12. Citations

• Sedra, A. S. & Smith, K. C. (2019). Microelectronic Circuits (8th ed.). Oxford University Press. Chapter 1: “Signals and Amplifiers” and the appendix on linear network theorems.
• Hayt, W. H., Kemmerly, J. E. & Durbin, S. M. (2018). Engineering Circuit Analysis (9th ed.). McGraw-Hill. The most-used undergraduate text for the mesh/nodal/Thevenin/Norton machinery.
• Irwin, J. D. & Nelms, R. M. (2020). Basic Engineering Circuit Analysis (12th ed.). Wiley.
• Boylestad, R. L. (2024). Introductory Circuit Analysis (14th ed.). Pearson. Strong on worked numerical examples.
• Nilsson, J. W. & Riedel, S. A. (2019). Electric Circuits (11th ed.). Pearson.
• Horowitz, P. & Hill, W. (2015). The Art of Electronics (3rd ed.). Cambridge University Press. The standard reference for practical engineering judgement around component selection, tolerance stack-up, and where textbook analysis collides with real hardware.
• Desoer, C. A. & Kuh, E. S. (1969). Basic Circuit Theory. McGraw-Hill. The classic rigorous treatment of Tellegen’s theorem and network-graph theory.
• Chua, L. O., Desoer, C. A. & Kuh, E. S. (1987). Linear and Nonlinear Circuits. McGraw-Hill. Definitive on linearisation, small-signal models, and Chua’s circuit.
• Nagel, L. W. (1975). SPICE2: A Computer Program to Simulate Semiconductor Circuits. ERL Memo ERL-M520, UC Berkeley. The original SPICE PhD thesis; foundation of every circuit simulator since.
• IEEE Std 315-1975 (R1993). Graphic Symbols for Electrical and Electronics Diagrams (Including Reference Designation Letters). Institute of Electrical and Electronics Engineers.
• IEC 60617 (continuously revised). Graphical symbols for diagrams. International Electrotechnical Commission. The international counterpart to IEEE 315.
• IEC 60063:2015. Preferred number series for resistors and capacitors. Source of the E-series values.
• ngspice project. ngspice User’s Manual, latest revision. https://ngspice.sourceforge.io/docs.html
• Linear Technology / Analog Devices. LTspice XVII Help and Reference.
• Williams, J. (ed., 1991). Analog Circuit Design: Art, Science and Personalities. Butterworth-Heinemann. Practitioner essays from the analog community’s leading designers — invaluable engineering-judgement context.