PCB Design
See also (Tier 3 family index): PCB Substrates
1. At a glance
A printed circuit board (PCB) is a layered glass-fibre / epoxy-resin substrate carrying patterned copper interconnect on one or more layers, with solder mask, silkscreen, plated through-holes (PTH), and (in modern designs) blind / buried / laser-drilled microvias. It is the mechanical and electrical platform on which every modern electronic product is built — the only ubiquitous alternative is the bond-wire-and-leadframe inside a chip package, and even that is now usually mounted onto a tiny PCB substrate before final encapsulation.
A PCB is simultaneously:
- The interconnect between components (the schematic, geometrically realised).
- The mechanical structure that holds them in place (often the structural chassis of small products — a phone PCB is the phone’s spine).
- The return-current network — every signal flows in a loop, and the board’s planes determine the loop geometry.
- The thermal path — for any device above a few hundred milliwatts the copper plane is part of the heatsink.
- The EMI / EMC element — what radiates, what couples, what passes regulatory pre-scan.
Engineering work breaks roughly five ways: stack-up + material selection, trace design (DC current, voltage clearance, controlled impedance), signal integrity (SI), power integrity (PI), and EMI/EMC + thermal layout. Modern boards above a few hundred megahertz or a few amps cannot be designed by following datasheet “evaluation board” copy-paste — the layout is the design. A circuit that works on a breadboard at DC will radiate, pick up noise, oscillate, fail conducted-emissions, and confuse the engineer’s debug session once it is built on a poorly-laid PCB.
This note builds on [[Engineering/circuit-analysis]], [[Engineering/op-amps]], [[Engineering/digital-logic]], [[Engineering/semiconductor-devices]], and [[Engineering/power-electronics]]. The signal-integrity equations originated in [[Engineering/electromagnetics-engineering]].
2. Why it matters — first principles
The breadboard-vs-PCB jump is where junior engineers run into a wall. Five physical facts cause it:
- A copper trace is not a wire. It is R + L + (mutual L to neighbours) + (C to neighbours and planes), distributed along its length. At DC the R term dominates; at MHz the L term dominates; above ~100 MHz the trace must be analysed as a transmission line with characteristic impedance Z₀.
- Loop area is an antenna aperture. Every current flows in a loop. The voltage induced in (or radiated from) a loop is proportional to dΦ/dt = A·dB/dt. Halve the enclosed area, halve the susceptibility and emissions.
- Return current follows least impedance, not least resistance. At DC, current spreads across a return plane minimising R. Above ~10 kHz it preferentially flows directly under the signal trace, because that minimises loop inductance. A slot or split in the return plane forces the current to detour — instantly creating a loop antenna.
- Decoupling is a local energy reservoir. A switching CMOS gate demands transient current in nanoseconds. The bulk supply is inductively too far away (μH of cable inductance) to deliver it in that time. The local 100 nF MLCC sources it; the bulk cap then recharges the MLCC over microseconds.
- The ground plane is doing four jobs simultaneously. Return path, shield, thermal spreader, mechanical reference. Treat it as one of those — say, “just ground” — and the other three quietly break.
These are not abstract concerns. Most products fail their first EMC pre-scan and their first thermal soak, and most of the fixes are layout changes that should have been done before fabrication.
3. Stack-up — the foundation
The stack-up — the order and thickness of copper and dielectric layers — is the single most consequential decision in a board’s design. Get it wrong and no amount of routing skill recovers signal integrity.
Common stack-ups
| Layers | Order (top → bottom) | Typical use |
|---|---|---|
| 2 | SIG / GND-fill — SIG / GND-fill | Hobby, simple analog, low-density digital ≤ 25 MHz |
| 4 | SIG — GND — PWR — SIG | The default for most consumer + industrial designs |
| 4 (SI-optimised) | SIG — GND — SIG — PWR/GND | Each signal layer has an adjacent return plane |
| 6 | SIG — GND — SIG — SIG — PWR — SIG | Mid-density; planes at L2 + L5, signal pairs L3/L4 swap reference |
| 6 (SI-optimised) | SIG — GND — SIG — GND — PWR — SIG | Better SI for high-speed inner layers |
| 8 | SIG — GND — SIG — GND — PWR — SIG — GND — SIG | High-speed digital (DDR4 + PCIe gen3) |
| 10–16 | Multiple PWR/GND pairs split by rail | Server motherboards, FPGA development boards |
The golden rule: every signal layer must have an adjacent reference plane (preferably GND, optionally PWR) within ≤ 0.2 mm. If the design uses both top and bottom for signals, the next layer in from each surface must be a continuous plane.
Material classes (IPC-4101 specification sheet numbers)
| Class | T_g (°C) | D_k @ 1 GHz | Loss tan (Df) | Examples | Used for |
|---|---|---|---|---|---|
| Standard FR-4 (IPC-4101 /21) | 130–140 | 4.2–4.5 | 0.020 | Isola 370HR, ITEQ IT-180A, Shengyi S1141 | < 100 MHz general, < 1 Gbps serial |
| High-T_g FR-4 (/24, /26, /98) | 170–180 | 4.0–4.4 | 0.015 | Isola 370HR-HT, Panasonic R-1755V | Lead-free assembly, automotive, industrial 105 °C |
| Mid-loss (/101) | 170 | 3.6–3.8 | 0.008 | Isola I-Speed, Panasonic Megtron 4 | 5–10 Gbps SerDes |
| Low-loss (/124, /126) | 180–200 | 3.4–3.6 | 0.004 | Panasonic Megtron 6, Isola Tachyon-100G, Nelco N4000-13 | 10–25 Gbps PCIe gen4 / 100GbE |
| Ultra-low-loss / RF (/240, /241) | 280+ (PTFE) | 2.5–3.5 | 0.001–0.003 | Rogers RO4350B, RO4003C, RO3003, RO6002, Taconic TLY-5, Arlon AD250 | mmWave, 5G, 24–77 GHz radar |
| Polyimide flex | 220 | 3.4–3.6 | 0.005 | DuPont Pyralux AP, Kapton HN | Flex / flex-rigid |
| Metal-core (MCPCB) | — | — | — | Bergquist T-Clad, Ventec VT-4B5 | High-power LED, EV power modules |
For typical mixed-signal industrial work, the workhorse is Isola 370HR or Shengyi S1000-2 / S1170G in the JLCPCB / PCBWay supply chain — high-T_g enough for RoHS reflow, cheap, and predictable.
Copper weights
| Notation | Thickness | Use |
|---|---|---|
| ½ oz | 17.5 μm (0.7 mil) | Inner layers, fine-line BGA escape |
| 1 oz | 35 μm (1.4 mil) | Default outer + general inner |
| 2 oz | 70 μm (2.8 mil) | Power planes, currents > 5 A |
| 3 oz | 105 μm (4.2 mil) | Heavy-current motor drives, battery management |
| 4–6 oz | 140–210 μm | Welder controllers, battery-pack BMS, EV inverter bus bars |
| 10+ oz | 350+ μm (“heavy copper”) | Custom — IPC-2152 deratings essential |
Beware: inner-layer finished copper after plating is typically 0.5 oz less than the starting foil (it does not get plated up). Outer-layer copper is plated up — request “1 oz outer” and you’ll receive 1.4–1.7 oz finished thickness once plating + HASL/ENIG is added.
Surface finish
| Finish | Cost | Shelf life | Flatness | Notes |
|---|---|---|---|---|
| HASL (lead) | $ | 12 mo | Poor | Cheap; uneven for fine-pitch BGA |
| Lead-free HASL | $ | 12 mo | Poor | RoHS-compliant; same flatness issues |
| ENIG (Ni/Au) | $$ | 12 mo+ | Excellent | Default for BGA / QFN ≤ 0.5 mm pitch; watch black-pad failure |
| ENEPIG (Ni/Pd/Au) | $$$ | 12 mo+ | Excellent | Higher-reliability ENIG variant; wire-bondable |
| OSP (organic) | $ | 6 mo | Excellent | Cheap, flat; oxidises if not soldered promptly |
| Immersion silver | $$ | 6–12 mo | Good | Tarnishes; whisker risk |
| Immersion tin | $$ | 6–12 mo | Good | Press-fit connectors |
| Hard gold (electrolytic) | $$$$ | Indefinite | Excellent | Edge connectors, key contacts |
4. Practical math / design equations
Trace current capacity (IPC-2152)
Modern IPC-2152 (replaces the older IPC-2221 nomograph) accounts for layer location (external vs internal), copper thickness, and ambient. Rough rules of thumb for 1 oz copper, external traces:
| ΔT (°C rise) | mil / A | mm / A |
|---|---|---|
| 10 | 6 mil / A | 0.15 mm / A |
| 20 | 3 mil / A | 0.075 mm / A |
| 30 | 2 mil / A | 0.05 mm / A |
For internal traces, derate by ~50 % (less natural convection). For 2 oz copper, divide width by ~1.6. Always check the IPC-2152 chart at your specific (copper weight, ΔT, layer) combination for any current ≥ 3 A.
Voltage clearance (IPC-2221B Table 6-1)
Working voltage between conductors, sea-level, B1 (external uncoated):
| V (DC + peak AC) | Min spacing |
|---|---|
| ≤ 15 V | 0.05 mm (2 mil) |
| 16–30 V | 0.1 mm (4 mil) |
| 31–50 V | 0.1 mm (4 mil) |
| 51–100 V | 0.6 mm (24 mil) |
| 101–150 V | 0.6 mm (24 mil) |
| 151–170 V | 1.25 mm (49 mil) |
| 171–250 V | 1.25 mm (49 mil) |
| 251–300 V | 1.25 mm (49 mil) |
| 301–500 V | 2.5 mm (98 mil) |
| 501+ V | +0.005 mm per V (0.2 mil/V) |
Conformal coat (B4) cuts these to roughly a third; coated inner layers (B2) similar. Mains-voltage creepage and clearance are then also governed by safety standards (UL 60950 / 62368, IEC 60664-1) and the relevant standard generally wins — usually 6–8 mm primary-to-secondary on an offline supply at 250 V_AC mains, far in excess of IPC.
Controlled impedance — microstrip and stripline
Single-ended microstrip (Hammerstad–Jensen approximation, signal layer over a reference plane separated by height h, trace width w, copper thickness t, dielectric εr):
Z₀ ≈ (87 / √(εr + 1.41)) · ln(5.98·h / (0.8·w + t)) Ω
Valid for 0.1 ≤ w/h ≤ 2.0.
Stripline (signal sandwiched between two reference planes, total dielectric thickness b):
Z₀ ≈ (60 / √εr) · ln(4·b / (0.67·π·(0.8·w + t))) Ω
Differential microstrip (two coupled traces, edge-to-edge separation s):
Z_diff ≈ 2 · Z₀ · (1 − 0.48·exp(−0.96·s/h)) Ω
Typical targets: 50 Ω single-ended (PCIe / SATA reference, RF), 100 Ω differential (USB, Ethernet, LVDS, PCIe), 85 Ω differential (USB 3.2 and PCIe gen3+ since the 2010 spec update — not 100 Ω, a frequent error), 90 Ω differential (USB 2.0).
For exact synthesis use a field solver (Polar Si9000, Saturn PCB Toolkit, Mentor HyperLynx LineSim, KiCad’s built-in calculator). Closed-form is good to ±5 %; high-speed sign-off needs 2D EM solution.
Propagation delay and the “is it a transmission line?” criterion
Propagation delay on FR-4 (εr ≈ 4.3) microstrip: t_pd ≈ 6 ps/mm (170 ps/inch). On stripline (fully embedded in dielectric): t_pd ≈ 7 ps/mm (180 ps/inch) — slower because of higher effective εr.
A trace must be treated as a transmission line if:
t_r < 2 · t_pd · ℓ → ℓ_critical = t_r / (2 · t_pd)
For CMOS with t_r = 1 ns: ℓ_critical ≈ 1000 ps / 12 ps/mm ≈ 83 mm (3.3 in). Modern 65 nm CMOS at t_r = 200 ps: ℓ_critical ≈ 17 mm (0.67 in) — almost every trace.
Via parasitics
| Parameter | Typical value |
|---|---|
| Via capacitance | 0.3–1 pF (depends on pad and antipad size) |
| Via inductance | ~1 nH per mm of via length |
| Via DC current capacity | 1–4 A (0.3 mm drill, 1 oz plating) |
| Stub length impact | 1 mm via stub adds ~3 ps/mm rise time degradation |
Back-drilling physically removes the unused portion of a through-hole via (the “stub”) on high-speed lines — required for ≥ 10 Gbps designs. Cost: +10–25 % fab. Microvias and skip-vias (HDI process) replace it on dense designs.
Crosstalk
For two parallel microstrip traces of length ℓ, spacing s, height h above plane, edge rate t_r:
NEXT ≈ (k_NE · V_aggressor) with k_NE = (1/4) · (C_m/C₀ + L_m/L₀) FEXT ≈ (1/2) · ℓ/t_pd · (L_m/L₀ − C_m/C₀) · V_aggressor / t_r
Practical rule: the 3W rule — keep centre-to-centre spacing ≥ 3× trace width to limit crosstalk to ~1 %. The 2W rule (centre-to-centre ≥ 2× width) is the more aggressive routing limit on dense boards.
5. Signal integrity — the modern lecture
When does it bite?
If your edge rate is faster than t_2pd of any trace on your board, you have an SI problem. With 2 ns rise time logic this means anything over ~165 mm; with 200 ps SerDes, anything over ~17 mm. Modern boards live in the second regime.
Termination strategies
| Topology | Pros | Cons |
|---|---|---|
| Source-series (R_s near driver, R_s + R_drv ≈ Z₀) | One resistor; no DC current; cheap | Half-amplitude wave during transit — only the receiver sees full swing |
| End parallel (R_t at receiver to GND or V_TT) | Full amplitude on the line; clean for multidrop receive | DC current draw; needs V_TT supply for split termination |
| Thévenin (split R to V_CC + GND) | Sets V_OH bias; clean | DC current; two resistors |
| AC termination (R + C at receiver) | No DC current | C must be sized for edge rate; some reflection at low frequencies |
| Diode clamp | Cheap; works on slow buses | Adds capacitance; doesn’t damp ringing |
DDR4 uses fly-by topology with V_TT = V_DDQ/2 parallel termination. PCIe uses AC-coupled point-to-point with internal driver termination. USB 2.0 uses 45 Ω source termination at the host. LVDS is current-mode driven into a 100 Ω termination at the receiver — no source termination needed.
Differential pair routing
- Intra-pair skew: keep ≤ 0.1× edge rate, typically ≤ 5 mil (0.13 mm) for USB 3, ≤ 2 mil for PCIe gen4+. Length-match with serpentine wiggles near the source of mismatch, not at the far end.
- Inter-pair skew (between byte lanes in DDR, between TX and RX of a SerDes): typically ≤ 5 ps for the same data word, can be relaxed for unrelated lanes.
- Bend rules: no 90° angles; use 45° chamfers or curves. Both traces of the pair should turn together to preserve the differential impedance through the bend.
- Via transitions: stitch ground vias within ~λ/20 of the signal via at the highest frequency of interest. For 10 GHz that’s ~1.5 mm.
- No via stubs on the differential path beyond a few hundred microns at 10 Gbps+ — back-drill or use HDI.
Reference-plane integrity
A signal that crosses a split or slot in its reference plane forces the return current to detour around the discontinuity. The detour creates a loop antenna and a large series inductance. Symptoms: failed EMC, ringing, ground bounce, mysterious crosstalk to unrelated traces hundreds of mils away.
Cure: don’t split planes. If a moat is unavoidable (truly isolated analog + digital domains), route signals over the moat at a single bridge with stitch capacitors (~10 nF MLCC) at the crossing — gives the AC return current a path while preserving DC isolation.
When a signal changes reference plane at a via (e.g. drops from L3 to L6 through a board with GND on L2 and L5), the return current must also change planes — through plane capacitance and through any stitch vias. Stitch a GND via within 1–2 mm of every signal-via that changes layers.
Eye diagrams and jitter budget
Above ~1 Gbps, link budgets are stated as eye-mask compliance. Total jitter budget is the sum of:
- Random jitter (RJ) — Gaussian, specified as σ; budget by RMS sum and convert to peak-peak at the target BER. At BER = 10⁻¹² that’s 14σ.
- Deterministic jitter (DJ) — duty-cycle distortion, ISI, periodic.
- Total = DJ + 14·σ_RJ at BER 10⁻¹².
PCIe gen4 (16 GT/s) tolerates ~0.30 UI total jitter at the receiver; trace + via + connector losses must leave headroom inside that. Pre-emphasis and equalisation (TX FFE, RX CTLE, DFE) recover signal that the channel has rolled off.
Topologies
| Name | Use | Notes |
|---|---|---|
| Point-to-point | PCIe, SATA, HDMI single-link, USB | Cleanest SI; cost 1 driver + 1 receiver per lane |
| Bussed (T-tree) | DDR1–DDR2, legacy SPI, I²C | Stubs ring; works only at low edge rates |
| Fly-by | DDR3, DDR4, DDR5 address / command | Series of receivers down a single trace, terminated at far end |
| Star | Some clock distribution | Each branch independent; matched stub lengths |
6. Power integrity (PDN)
PDN impedance target
A switching load draws transient current I_trans with rise time t_r. The PDN must hold V_supply to within ΔV_max during that transient:
Z_target(f) = ΔV_max / I_trans where f_max ≈ 0.35 / t_r
Example: a 1 V CPU rail at 50 A peak transient with a 5 % ripple budget → ΔV = 50 mV, Z_target = 50 mV / 50 A = 1 mΩ from DC up to ~350 MHz (for t_r = 1 ns). Achieving 1 mΩ to 350 MHz is genuinely hard and is the entire problem of high-end CPU/FPGA power delivery.
Decoupling cascade
| Frequency band | Component | Typical value | Quantity |
|---|---|---|---|
| DC – 1 kHz | Bulk electrolytic / polymer | 100–1000 μF | 1–2 per rail |
| 1 kHz – 100 kHz | Tantalum polymer / OS-CON | 22–100 μF | 2–4 per IC |
| 100 kHz – 10 MHz | MLCC X7R 1 μF, 4.7 μF | 1–4.7 μF | 2–6 per IC |
| 10 MHz – 200 MHz | MLCC X7R 100 nF | 100 nF | 1 per IC power pin |
| 200 MHz – 1 GHz | MLCC C0G 1–10 nF | 1–10 nF | Selectively, at hot pins |
| > 1 GHz | Plane capacitance, intrinsic | — | Designed in stack-up |
Murata GCM and TDK CGA are the automotive-grade MLCC workhorses for the 100 nF / 1 μF / 10 μF range. Use X7R dielectric for general bulk; C0G/NP0 for the smallest, lowest-tolerance HF caps where DC-bias derating is unacceptable. Watch the DC bias derating on X5R / X7R — a 0805 22 μF X5R rated 10 V can collapse to 4 μF at 5 V DC bias.
Anti-resonance and capacitor mixing
Two capacitors in parallel — one ceramic (resonant at, say, 20 MHz) and one bulk polymer (resonant at, say, 1 MHz) — produce anti-resonance between their self-resonant frequencies, where they look mutually inductive and the parallel impedance peaks. The cure is to fill the valley with intermediate values and to spread part counts (5 × 100 nF is broader-band than 1 × 500 nF).
Plane capacitance
Two parallel power-plane layers separated by dielectric thickness h, area A:
C_plane = ε₀ · ε_r · A / h [F]
A typical 100 × 100 mm pair of inner planes 0.1 mm apart on FR-4 (ε_r = 4.3) gives C ≈ 380 pF. Useful at GHz, where MLCC ESL turns conventional decoupling into an inductor.
Buried-capacitance laminates (3M C-Ply, Sanmina ZBC-1000, Oak-Mitsui FaradFlex) put 50 μm or less of high-εr dielectric between PWR and GND planes for ~1 nF per square inch — sometimes eliminates the smallest decoupling caps entirely.
7. EMI / EMC at layout time
Loop area is everything
Every current loop is an antenna. Halve the loop area, halve the radiation. Practical mandates:
- Route every high-speed signal directly over its return reference plane at minimum trace-to-plane spacing.
- Place decoupling capacitors adjacent to the IC power pin, with the cap’s GND pad joined to the GND plane through its own via — not the IC’s GND via.
- Keep switching loops in power converters (V_in cap → switch → return) sub-millimetre. See
[[Engineering/power-electronics]]§3 worked examples.
The 20H rule
Recess the power plane by 20× the plane-to-plane dielectric thickness inward from the board edge. Reason: at the edge of the board the PWR and GND planes form a fringing-field cavity that radiates the plane-resonance modes (~ tens of MHz to a few GHz). Pulling PWR back 20H — typically 1–2 mm on standard FR-4 — drops edge radiation by ~70 %. Add edge-stitching vias every λ/20 along the perimeter (typically 5–10 mm spacing) to short the cavity modes.
Ground splits — almost always wrong
The textbook “split your analog and digital grounds and join them at one star point” was correct in the 1980s when ADCs ran at kHz rates. With modern Σ-Δ ADCs, mixed-signal SoCs, and switching supplies on the same board, a unified ground plane is almost always superior — Henry Ott devotes an entire chapter to this in EMC Engineering. The exceptions are isolated medical instrumentation and low-noise scientific instruments with truly separate domains.
If you must split: only the GND plane, never PWR; cross signals over the split at exactly one location; bridge the split with high-Q ferrite (not a wire) if mid-frequency isolation is wanted.
Cable interfaces
Any cable leaving the board is an antenna — and the most likely radiator that fails EMC. Mandatory at every interface:
- Common-mode choke (Würth WE-CMB, TDK ACT45B) on power and high-speed signal cables.
- TVS diodes for ESD (Würth WE-TVS, Nexperia PESD series).
- Bulk capacitance (Y-rated caps to chassis for offline supplies; ordinary MLCC for low-voltage).
- Shield-pigtail discipline: shielded cables must terminate to the chassis with a 360° connection, not a pigtail wire (“pigtailing” raises the impedance of the shield connection by 30 dB at 100 MHz and effectively unshields the cable).
Ferrite bead caveat
A ferrite bead (e.g. Würth WE-CBF, Murata BLM18 / BLM21) looks resistive at its rated frequency but is inductive below that frequency. Inserted between a switching regulator and a quiet rail, it forms an LC resonator with the downstream decoupling caps that can ring at MHz frequencies and amplify noise instead of attenuating it. Datasheet plots S21 vs frequency — use them. If a bead is needed in a sensitive analog rail, damp the LC with a series 1–2 Ω or a small parallel R.
EMC pre-scan
| Tool | Use |
|---|---|
| Beehive Electronics 100-series near-field probes | Find radiating spots on a prototype |
| Langer EMV-Technik probe kit | Higher-end near-field investigation |
| TEM cell (e.g. Schwarzbeck TEM 250) | Small-board pre-compliance radiated emissions |
| GTEM cell (TESEQ / FCC) | Larger; up to 18 GHz |
| Spectrum analyzer (R&S FSV, Keysight N9020) | Conducted + radiated capture |
| LISN (R&S ENV216, Solar Electronics) | Conducted-emissions test method |
| ESD gun (Teseq NSG 437) | IEC 61000-4-2 immunity check |
A two-day in-house pre-scan with near-field probes + LISN + spectrum analyzer catches >80 % of EMC failures before the formal test-lab visit at $2500 / day.
8. Thermal layout
Heat exits a chip three ways
- Through the die-attach pad to the PCB (θ_JB — junction-to-board). Dominant for QFN, BGA, D-PAK with exposed pad on a copper plane.
- Through the package top to ambient (θ_JA — junction-to-ambient natural convection). Small ICs without thermal pad.
- Through a heatsink on top of the package (θ_JC + θ_CS + θ_SA). Larger power devices.
For a typical surface-mount package with an exposed pad, the PCB copper is the heatsink — there is no separate heatsink. The size of the copper pour and the connection to internal planes via thermal vias determines θ_JA more than any other factor.
Thermal vias
Under a QFN / D-PAK / D²PAK / PowerSO exposed pad, drop an array of vias to inner copper planes:
| Parameter | Typical |
|---|---|
| Drill diameter | 0.3 mm (12 mil) |
| Pitch | 1.0 mm grid (30–40 mil) |
| Plating | 25 μm copper barrel (1 oz wall) |
| θ_via | ~70 °C/W per via in still air |
| Array of 12 vias | ~5.8 °C/W in parallel |
Capping: leave thermal vias open (vendors call this “Type II” or “open vias”) for low-cost boards; tent the back side (“Type IV” / via-in-pad with epoxy fill + plating) for BGA where solder would otherwise be wicked away through the via.
Junction temperature target
T_j,max from datasheet (typically 150 °C silicon, 175 °C SiC, 200 °C GaN) — derate to 125 °C operating maximum for reliability. Junction temperature:
T_j = T_amb + P · (θ_JA)
Example: a TPS54331 buck dissipating 0.6 W in a SO-8 PowerPad on 1 sq inch of 1 oz copper, θ_JA ≈ 36 °C/W → ΔT = 22 °C; in 70 °C ambient that’s T_j = 92 °C. Comfortable.
Without the copper pour, θ_JA balloons to ~100 °C/W → ΔT = 60 °C → T_j = 130 °C in the same ambient. Same chip, same circuit, different layout, different reliability.
IR camera + thermocouple validation
A FLIR E-series or similar thermal camera ($2–8k) saves orders of magnitude of debug time on every prototype. Pair with a fine-wire thermocouple (TC Direct K-type 0.13 mm) for spot validation — IR alone can mislead on shiny copper (low emissivity, reads cold). Paint hot spots flat black or apply matte tape for accurate readings.
9. Worked examples
Example A — Buck regulator layout, 12 V → 3.3 V @ 5 A, 500 kHz
(Electrical design follows [[Engineering/power-electronics]] §3 worked example 1; layout below.)
Critical loop: V_in capacitor → high-side MOSFET → low-side MOSFET → GND → back to V_in cap. di/dt during a switching edge is ~0.5 A/ns; with 5 nH of parasitic loop inductance that’s V_spike = L·di/dt = 5 nH · 0.5 A/ns = 2.5 V ringing on the 12 V rail. To keep V_spike < 1 V we need < 2 nH, which means:
- The 4× 10 μF X7R input MLCC must be within 2 mm of the switch IC V_IN pins, on the same side of the board.
- The cap’s GND vias must join the same inner GND plane within 0.5 mm.
- No “neck-down” of the input copper from cap to IC.
Switch-node copper: a tradeoff. Small SW copper = high impedance = ringing. Large SW copper = low impedance but radiating area (the SW node is the noisiest node by far, swinging 12 V at hundreds of MHz). Sweet spot for a 5 A buck: 50–100 mm² SW copper, kept on the top layer only (no via-stitched flooding), shielded by adjacent GND copper on the same layer with the 3W spacing rule.
Output stage (inductor, output caps): much less critical because the inductor smooths the di/dt. Still put the output caps within ~5 mm of the inductor; route the feedback sense as a Kelvin trace from the output cap (not the inductor) back to the FB pin.
Trace widths: 5 A at 10 °C rise (1 oz outer) needs 75 mil (1.9 mm) per IPC-2152. For the input/output current path use solid pour rather than a defined trace.
Thermal vias under the buck IC exposed pad: 3×4 array of 0.3 mm vias on 1 mm pitch = 12 vias → ~6 °C/W in parallel to the inner GND plane.
Feedback routing: keep the FB trace short, narrow (10–15 mil), and away from the SW node by at least 3× spacing. Sense at the load if remote regulation matters (run separate sense traces from the load point and Kelvin them at the FB divider).
Example B — DDR4 fly-by topology, 1600 MT/s (800 MHz)
DDR4 SDRAM eliminates the T-topology of DDR2 in favour of fly-by addressing — the address / command / control signals (CA/CTL) hop sequentially from one DRAM to the next down a series-terminated daisy-chain on the module.
Why fly-by replaced T-tree (around DDR3-1066, mid-2000s): in a T-tree, the controller drives a branched path that creates stub reflections at every receiver. Above ~533 MT/s these reflections close the eye. Fly-by sees the signal pass each receiver only once with a controlled-impedance termination at the end — clean SI at 3200 MT/s and beyond.
Cost of fly-by: the addresses arrive at each DRAM at different times — first DRAM sees them first, last DRAM ~500 ps later. The controller compensates by DQ write leveling at boot — it trains the DQ launch timing per byte lane to match the staggered CA arrival. Length-matching of CA traces becomes less critical (fly-by inherently mismatches them), but length-matching of DQ within a byte lane is essential because there’s no per-lane training there.
Layout rules (typical for 1600 MT/s):
| Group | Length match | Notes |
|---|---|---|
| DQ within byte lane (DQ0..DQ7 + DQS + DM) | ±5 mil (±0.13 mm) | Strict — per-lane training only |
| Address/command (fly-by) | ±100 mil cumulative end-to-end | Trained at boot |
| Clock (CK + CK#) | ±5 mil | Critical |
| Byte-lane to byte-lane | ±50–100 mil | Looser |
Reference VTT termination: parallel termination at the end of the fly-by chain to V_TT = V_DDQ/2 = 0.6 V. A dedicated VTT regulator (e.g. TI TPS51200) sources or sinks current to hold V_TT during writes and reads. Bypass with 4–6 × 0.1 μF MLCC.
Example C — USB 2.0 high-speed differential pair (480 Mbps), 4-layer board
USB 2.0 high-speed signalling: 480 Mbps NRZ, 90 Ω ± 15 % differential impedance from PHY to connector. Rise time ~500 ps. Critical length where transmission-line effects bite: ~80 mm (3.1 in) — typical phone-PCB length, so always treat as transmission line.
Stack-up: standard 4-layer 1.6 mm FR-4 board.
| Layer | Function | Thickness |
|---|---|---|
| L1 (top) | Signal | 35 μm Cu |
| Prepreg | Dielectric | 0.36 mm (εr ≈ 4.3) |
| L2 | GND plane | 35 μm Cu |
| Core | FR-4 | 0.83 mm |
| L3 | PWR plane | 35 μm Cu |
| Prepreg | Dielectric | 0.36 mm |
| L4 (bottom) | Signal | 35 μm Cu |
Trace dimensions (microstrip on L1 over GND on L2, εr = 4.3, h = 0.36 mm):
Using the differential-microstrip approximation:
Z_diff ≈ 2 · Z₀ · (1 − 0.48·exp(−0.96·s/h))
Target Z_diff = 90 Ω. From single-ended microstrip with w = 0.20 mm (8 mil), h = 0.36 mm, t = 35 μm:
Z₀ ≈ (87 / √(4.3 + 1.41)) · ln(5.98·0.36 / (0.8·0.20 + 0.035)) Z₀ ≈ (87 / 2.39) · ln(2.155 / 0.195) Z₀ ≈ 36.4 · ln(11.05) = 36.4 · 2.40 = 87.4 Ω single-ended
Differential with s = 0.20 mm (8 mil) edge-to-edge:
Z_diff ≈ 2 · 87.4 · (1 − 0.48·exp(−0.96 · 0.20/0.36)) = 174.8 · (1 − 0.48·exp(−0.533)) Z_diff ≈ 174.8 · (1 − 0.48·0.587) = 174.8 · 0.718 = 125 Ω — too high.
Iterate: increase w to 0.30 mm (12 mil), keep s = 0.20 mm:
Z₀ ≈ 36.4 · ln(5.98·0.36 / (0.8·0.30 + 0.035)) = 36.4 · ln(2.155 / 0.275) = 36.4 · 2.06 = 75 Ω Z_diff ≈ 2·75·0.718 = 108 Ω — closer.
Final iteration with field solver (Polar Si9000): w = 0.34 mm (13.4 mil), s = 0.20 mm (8 mil) → Z_diff = 90.5 Ω, comfortably in spec.
Length match: USB 2.0 HS spec allows ±50 mil within the pair — generous for 480 Mbps.
Bend rules: 45° chamfers; both traces of the pair bend simultaneously, preserving s through the corner. No 90° angles. No via stubs longer than 0.5 mm on the differential path (USB 2.0 is forgiving compared to USB 3, but stubs reflect anyway).
Reference plane continuity: keep the pair on L1 from end to end. Crossing onto L4 requires two signal vias + two stitching GND vias (one per signal via) within 1 mm to give the return current a path through plane capacitance.
ESD protection: place TVS diodes (e.g. Nexperia PESD2USB30A) within 5 mm of the connector. Trace from connector to TVS to PHY in that order — the diode must see the strike before the PHY does.
10. Tools
Schematic + layout (ECAD)
| Tool | Cost | Strengths |
|---|---|---|
| Altium Designer | $$$$ ($9k+ subscription) | Dominant commercial; deep BOM, ECAD-MCAD bridge, native 3D |
| Cadence Allegro / OrCAD | $$$$$ | High-end; rigid-flex, advanced SI, dominant in mil-aero |
| Mentor Xpedition (Siemens EDA) | $$$$$ | Constraint-driven routing; large-team flow |
| KiCad | Free | Open-source; rapidly closing the gap; v8+ usable for production |
| EasyEDA | Free / SaaS | Browser-based; integrated with JLCPCB part library |
| Autodesk Fusion Electronics (was Eagle) | $ | Legacy hobbyist; deprecated for serious work |
| Diptrace | $$ | Capable, lower-cost commercial alternative |
Signal integrity / power integrity
| Tool | Vendor | Use |
|---|---|---|
| Polar Si9000 + Speedstack | Polar Instruments | Field solver for impedance + stack-up; industry-standard at fab houses |
| Mentor HyperLynx SI / PI | Siemens | SI + PDN simulation pre-layout and post-layout |
| Ansys SIwave / HFSS | Ansys | 3D EM full-wave for high-end SI (10G+) |
| Cadence Sigrity (PowerSI, PowerDC, OptimizePI) | Cadence | The Cadence-flow PI/SI tool family |
| Keysight ADS | Keysight | RF + SerDes simulation; channel simulator + IBIS-AMI |
| CST Studio | Dassault Systèmes | 3D EM (now Simulia) |
| Sonnet | Sonnet | Planar EM for RF |
| openEMS | Open-source | FDTD EM solver |
Thermal
| Tool | Vendor | Use |
|---|---|---|
| Siemens Simcenter FLOEFD (was Mentor FloTHERM) | Siemens | Electronics CFD; chassis + board-level |
| Ansys Icepak | Ansys | Electronics thermal + EM coupled |
| 6SigmaET | Future Facilities (Cadence) | Purpose-built electronics CFD |
| COMSOL Multiphysics | COMSOL | Coupled thermal-electrical-mechanical |
DRC + manufacturability
| Tool | Use |
|---|---|
| ECAD built-in DRC (Altium, KiCad, Allegro) | First-pass design rules |
| Valor NPI (Siemens) | DFM check used by fab houses |
| DesignSpark PCB Insight | Free DFM checker |
| Sierra Circuits Better DFM | Free, web-based |
Component libraries
| Source | Notes |
|---|---|
| SnapEDA | Symbols + footprints + 3D for major parts; free tier |
| UltraLibrarian | Manufacturer-sponsored; broad and accurate |
| Component Search Engine (SamacSys) | Symbols + footprints + 3D, vendor-funded |
| Manufacturer-provided | Best source for niche parts (TI, ADI, Murata) |
Fab houses (capability matrix, typical at end-2025)
| Fab | Cheapest 2-layer | Min trace/space | Min drill | Controlled impedance | HDI / blind+buried | Lead time |
|---|---|---|---|---|---|---|
| JLCPCB | $2 / 5 pcs | 3.5/3.5 mil | 0.15 mm | ±10 % standard | yes (extra cost) | 3–5 d |
| PCBWay | $5 / 5 pcs | 3/3 mil | 0.1 mm | ±10 % | yes | 3–6 d |
| OSH Park | $5 / sq in (3 pcs) | 5/5 mil | 0.25 mm | no | no | 12 d |
| Sierra Circuits | $$$ | 2.5/2.5 mil | 0.075 mm laser | ±5 % | yes, full HDI | 24 h–5 d |
| Royal Circuit Solutions | $$$ | 2/2 mil | 0.075 mm | ±5 % | yes | 24 h–5 d |
| Advanced Circuits | $$$ | 3/3 mil | 0.1 mm | ±5 % | yes | 24 h–5 d |
| Multi-CB / Multek (DE / EU) | $$$ | 3/3 mil | 0.1 mm | ±7 % | yes | 1–2 wk |
JLCPCB and PCBWay dominate the prototype-to-low-volume market; Sierra, Royal, and Advanced are the US choices when ITAR, IPC Class 3, or short-turn HDI matter.
11. Cross-references
[[Engineering/circuit-analysis]]— Kirchhoff laws + Thévenin foundations for impedance work[[Engineering/ac-analysis-three-phase]]— line-frequency power distribution context[[Engineering/semiconductor-devices]]— switching devices that drive layout-critical loops[[Engineering/op-amps]]— gain-bandwidth-limited circuits requiring layout discipline[[Engineering/digital-logic]]— CMOS edge rates and signal-integrity origin[[Engineering/power-electronics]]— buck/boost/flyback layouts with worked switch-node math[[Engineering/electromagnetics-engineering]]— transmission line, radiation, and EMI theory- planned
[[Engineering/microcontrollers]]— typical MCU peripheral layout patterns - planned
[[Engineering/realtime-embedded]]— bring-up + debug of a populated PCB - planned
[[Engineering/fpga-design]]— BGA escape, DDR, high-speed serial layout
12. Citations
- Johnson, H. W. and Graham, M. High-Speed Digital Design: A Handbook of Black Magic, Prentice Hall 1993. The canonical SI text — still indispensable.
- Johnson, H. W. and Graham, M. High-Speed Signal Propagation: Advanced Black Magic, Prentice Hall 2003. The follow-up; modern multi-Gbps interconnect.
- Bogatin, E. Signal and Power Integrity — Simplified, 3rd ed., Prentice Hall 2018. The clearest practical SI / PI textbook in print.
- Ott, H. W. Electromagnetic Compatibility Engineering, 2nd ed., Wiley 2009. Definitive EMC reference for board + system design.
- Ott, H. W. Noise Reduction Techniques in Electronic Systems, 2nd ed., Wiley 1988. Older but still relevant for analog + grounding.
- Montrose, M. I. Printed Circuit Board Design Techniques for EMC Compliance, 2nd ed., IEEE Press 2000.
- Williams, T. EMC for Product Designers, 5th ed., Newnes 2017. EU-perspective regulatory + design overview.
- Hall, S. H., Hall, G. W., McCall, J. A. High-Speed Digital System Design, Wiley 2000.
- IPC-2221B:2012 — Generic Standard on Printed Board Design (the master design standard).
- IPC-2222A:2010 — Sectional Design Standard for Rigid Organic Printed Boards.
- IPC-2152:2009 — Standard for Determining Current-Carrying Capacity in Printed Board Design.
- IPC-A-600K:2020 — Acceptability of Printed Boards (the inspection criteria).
- IPC-A-610H:2020 — Acceptability of Electronic Assemblies (post-assembly inspection).
- IPC-6012F:2023 — Qualification and Performance Specification for Rigid Printed Boards.
- IPC-7351C:2024 — Generic Requirements for Surface Mount Design and Land Pattern Standard.
- IPC-4101F:2021 — Specification for Base Materials for Rigid and Multilayer Printed Boards.
- JEDEC J-STD-001H:2020 — Requirements for Soldered Electrical and Electronic Assemblies.
- JEDEC JESD51 series — Thermal characterization of integrated-circuit packages (JESD51-1 through JESD51-14).
- IEC 60664-1:2020 — Insulation coordination for equipment within low-voltage supply systems (mains-voltage clearance + creepage).
- UL 62368-1, 3rd ed., 2019 — Audio/video and IT equipment safety (replaces UL 60950).