Power Electronics
See also (Tier 3 family index): Battery Chemistries
1. At a glance
Power electronics is the controlled transfer of energy from one electrical form to another using switching semiconductors. It is the bridge between every primary power source (mains grid, battery, photovoltaic array, fuel cell, generator) and every load that demands a different voltage, frequency, or waveform than that source naturally supplies. There are four canonical converter families, and almost every real product is a chain of them:
- DC/DC converters — point-of-load supplies on a board (12 V → 1.0 V CPU core), battery management (4.2 V cell → regulated bus), isolated supplies (USB-PD bricks, telecom −48 V → 12 V intermediate-bus). Power range: milliwatts (energy harvesting) to megawatts (HVDC interconnects).
- DC/AC inverters — three-phase motor drives, solar string inverters, uninterruptible power supplies (UPS), EV traction inverters, wind-turbine grid-tie. Generate a sinusoidal (or quasi-sinusoidal) waveform from a DC bus.
- AC/DC rectifiers — offline supplies (the front end of every wall plug), battery chargers, EV onboard chargers (OBC), grid-tie active front-ends. Modern designs nearly always include power factor correction (PFC) to draw sinusoidal current.
- AC/AC converters — direct AC-to-AC at different frequency or amplitude. Cycloconverter (low-frequency output, used in giant ball-mill drives and ship propulsion); matrix converter (compact, no DC link, niche aerospace + research); back-to-back DC link (the practical answer 95 % of the time, two converters stitched at a DC bus). Solid-state transformers (SST) are the emerging member.
Modern power electronics depends on hard-switched and soft-switched topologies built from MOSFETs, IGBTs, GaN HEMTs, and SiC MOSFETs running at switching frequencies from line-frequency 50/60 Hz (thyristor rectifiers, phase-controlled) up to ~5 MHz (GaN resonant converters in small adapters). Engineering work consistently splits into four entangled domains:
- Topology + control choice — pick the family (buck, boost, flyback, LLC, PSFB, three-phase inverter), pick voltage-mode vs current-mode vs hysteretic vs digital-direct control, pick CCM vs DCM operation.
- Magnetics design — inductors and transformers are almost never off-the-shelf above a few amps and a few hundred kilohertz; you specify core material, geometry, turns, gap, wire gauge, and Litz strategy.
- Thermal / cooling — every watt lost in a semiconductor must leave through a junction-to-case-to-sink-to-ambient path with finite °C/W. Cooling dictates the package, layout, and often the final form factor.
- EMI mitigation — switching produces conducted noise (CISPR 11/22/32) on the input + output lines and radiated noise (30 MHz–6 GHz). Filtering, layout, shielding, and snubbers consume 10–25 % of the BOM and at least that fraction of the schedule.
A useful mental model: power electronics looks easy on paper (V_out = D × V_in is a one-line equation) and is brutal on the bench. The waveforms in the datasheet are averaged; the real switching node has 100 V/ns edges, 50 MHz ringing, and a thermal time constant of milliseconds. Most products fail their first EMC scan and their first thermal soak, and a senior engineer is mostly distinguished by spending less time fixing them.
This note builds directly on [[Engineering/semiconductor-devices]] (the switches), [[Engineering/electric-motors]] (the dominant high-power load), and [[Engineering/transformers-power-systems]] (the isolation in offline converters and the grid context).
2. First principles
Switch-mode operation. A power transistor (MOSFET, IGBT, BJT in old equipment) is operated only in the fully ON (V_DS ≈ 0, large I_D) or fully OFF (V_DS = bus, I_D = 0) states. Either state dissipates near-zero power: in ON, V_DS×I_D = (I_D · R_DS(on))·I_D = I²·R_DS(on), which a few-milliohm device makes small; in OFF, leakage current I_DSS · V_DS is negligible. The losses live in the transition between the two states — during the rise/fall, V and I are both nonzero. That’s why switching speed sets switching loss, and why fast wide-bandgap devices (SiC, GaN) directly translate into either higher efficiency or higher frequency.
Energy storage. Switching shovels energy between inductors (E_L = ½ L I²) and capacitors (E_C = ½ C V²) once per cycle. The ideal inductor + ideal capacitor + ideal switch makes a 100 %-efficient converter. Real inefficiency is just the sum of parasitic losses (R_DS(on), V_F, core loss, copper loss, ESR) — there is no fundamental loss mechanism the way there is in a linear regulator (which fundamentally dumps (V_in − V_out) × I_out as heat).
Volt-second balance. In steady state, the average voltage across any inductor in a switching converter is zero. Otherwise current would diverge. Equivalently for one cycle of period T:
∫₀ᵀ v_L(t) dt = 0 → V_on · t_on + V_off · t_off = 0
For a buck CCM: V_on = V_in − V_out (during switch ON); V_off = −V_out (during switch OFF). Setting volt-seconds equal: (V_in − V_out)·D·T = V_out·(1−D)·T → V_out = D · V_in. Every CCM topology relation falls out of this one identity.
Charge balance. Likewise, the average current through any capacitor in steady state is zero: ∫₀ᵀ i_C(t) dt = 0. This sets the relationship between input/output current and DC duty cycle.
Duty cycle D = t_on / T_sw. The single most important parameter in a converter — it sets the voltage ratio, the inductor ripple, the device stress, the magnetics size. Range typically 0.05–0.95; the controller saturates near the extremes.
CCM vs DCM. In Continuous Conduction Mode the inductor current never reaches zero in a cycle (heavy load). In Discontinuous Conduction Mode the inductor current hits zero, the diode turns off, and the switch node floats (light load). The boundary is BCM (Boundary Conduction Mode), where I_L touches zero exactly at the end of each cycle. The voltage gain equation, control-to-output transfer function, and loop dynamics are all different between CCM and DCM; a control loop tuned in CCM can ring or oscillate in DCM if not designed for both.
Switching loss. During turn-on or turn-off, V_DS and I_D overlap for ~(t_r + t_f). Approximate energy per transition:
E_sw ≈ ½ · V_DS · I_D · (t_r + t_f)
Total switching loss P_sw = E_sw · f_sw. This is linear in switching frequency and is the reason high-frequency converters need soft-switching (ZVS/ZCS) or wide-bandgap devices.
Conduction loss.
P_cond,MOS = I_RMS² · R_DS(on)·(T_j) (MOSFET — purely resistive) P_cond,IGBT = V_CE(sat) · I_avg + r_CE · I_RMS² (IGBT — diode-like drop + slope) P_cond,diode = V_F · I_avg + r_d · I_RMS²
R_DS(on) typically rises ~1.5–2× from 25 °C to 125 °C — always compute conduction loss at hot junction temperature, not at the datasheet headline 25 °C value.
Soft switching. Zero Voltage Switching (ZVS) turns the device on while V_DS is forced to zero by an external resonant network (LLC, phase-shift full bridge). Zero Current Switching (ZCS) turns the device off while I_D is zero. Either eliminates the V·I overlap loss and the dv/dt-induced EMI. The cost is a more complex topology + control + a load range over which ZVS is achievable.
3. Practical math / design equations
Buck converter (step-down DC/DC, V_out < V_in)
CCM voltage gain: V_out = D · V_in.
Peak-to-peak inductor ripple current:
ΔI_L = (V_in − V_out) · D · T_sw / L = (V_in − V_out) · D / (L · f_sw)
Typical design target: ΔI_L = 20–40 % of I_out,max. Lower ripple = larger L, higher cost. Higher ripple = smaller L but higher RMS currents and worse EMI.
Output voltage ripple (assuming ESR-free ceramic output cap, capacitor-dominated):
ΔV_out = ΔI_L / (8 · f_sw · C_out)
ESR-dominated: ΔV_out ≈ ΔI_L · ESR. Always compute both and take the larger — ceramic caps win on ESR but lose on capacitance at DC bias (an X7R 22 µF 0805 can drop to 4 µF at 5 V DC).
Peak inductor current: I_L,peak = I_out + ΔI_L/2. Inductor saturation must be > I_L,peak with margin — once an inductor saturates, L collapses and current spikes destroy the switch in microseconds.
Worked example 1 — buck, 12 V → 3.3 V, 5 A, 500 kHz
D = V_out / V_in = 3.3 / 12 = 0.275.
Choose ΔI_L = 30 % · I_out = 1.5 A:
L = (V_in − V_out) · D / (ΔI_L · f_sw) = (12 − 3.3) · 0.275 / (1.5 · 500e3) L = 8.7 · 0.275 / 7.5e5 = 2.394 / 7.5e5 = 3.19 µH
Pick a standard value: 3.3 µH (Coilcraft XAL5030-332, I_sat = 14.5 A, DCR = 11 mΩ — comfortable margin).
Peak inductor current: 5 + 1.5/2 = 5.75 A → well below 14.5 A saturation.
Output cap for 50 mV ripple (ESR-free assumption):
C_out ≥ ΔI_L / (8 · f_sw · ΔV_out) = 1.5 / (8 · 500e3 · 0.050) = 7.5 µF
In practice use 2 × 22 µF X7R 0805 (44 µF nominal, ~20 µF after 3.3 V DC derating + ESR < 5 mΩ) — gives plenty of margin and handles transient response.
MOSFET selection: high-side conducts I_RMS² ≈ D · I_out² → I_RMS,HS = √D · I_out = √0.275 · 5 = 2.62 A. Budget 1 W conduction → R_DS(on)(hot) ≤ 1 / 2.62² = 146 mΩ. Cold R_DS(on) ≤ 73 mΩ (1.5–2× hot/cold ratio). Pick TI CSD17483F4 (30 V, 35 mΩ max at V_GS = 4.5 V) or Vishay SiSS72DN. Switching loss at 500 kHz with t_r + t_f ≈ 10 ns: P_sw ≈ ½ · 12 · 5 · 10e-9 · 500e3 = 0.15 W — negligible at this frequency, dominated by conduction.
Synchronous low-side: same device family; conducts (1−D) · I_out² RMS = √0.725 · 5 = 4.26 A, larger conduction loss; but switching loss is essentially zero (turns on/off near zero V_DS due to body-diode commutation). Pick the lowest-R_DS(on) part that fits.
Boost converter (step-up DC/DC, V_out > V_in)
CCM voltage gain: V_out = V_in / (1 − D).
Inductor ripple: ΔI_L = V_in · D / (L · f_sw).
Right-half-plane (RHP) zero in control-to-output: ω_RHPZ = R_load · (1−D)² / L. The boost loop bandwidth is hard-capped at ~⅓ of ω_RHPZ — push it higher and the loop becomes non-minimum-phase unstable. This is why boost converters feel sluggish on transient response and why we limit them to ≤ ~5× boost ratios in practice.
Buck-boost (inverting, V_out polarity flipped)
V_out = −V_in · D / (1 − D). Same RHP-zero pathology as boost.
Flyback (transformer-isolated buck-boost)
V_out = V_in · D / (n · (1 − D)), n = N_p / N_s (primary-to-secondary turns ratio).
Primary peak current (CCM):
I_p,peak = (I_out / n) / (1 − D) + ΔI_p / 2
In DCM (typical for small flybacks ≤ 30 W):
I_p,peak = √(2 · P_out / (η · L_p · f_sw)) · 1 / D
Primary inductance for DCM operation at maximum load:
L_p = (V_in,min · D_max)² / (2 · P_in,max · f_sw)
Worked example 2 — flyback, 90–265 V_AC → 24 V at 2 A, 65 kHz
P_out = 48 W. Assume η = 0.88 → P_in = 54.5 W.
After universal-input bridge rectifier with 100 µF bulk cap, V_in,DC ranges roughly 100 V (90 V_AC line trough) to 375 V (265 V_AC peak).
Design choice: DCM, D_max = 0.45 at V_in,min.
Reflected output voltage V_OR (across primary when secondary is conducting): set V_OR = V_out · n. Choose so the MOSFET sees V_DS,max = V_in,max + V_OR + V_leakage_spike ≤ 80 % of breakdown. For a 700 V CoolMOS:
V_OR ≈ 700·0.8 − 375 − 100 (leakage) ≈ 85 V → n = V_OR / V_out = 85 / 24 ≈ 3.5
Round to a turns ratio with practical secondary turns: pick N_p / N_s = 18 / 5 = 3.6.
Primary inductance:
L_p = (V_in,min · D_max)² / (2 · P_in · f_sw) = (100 · 0.45)² / (2 · 54.5 · 65e3) L_p = 2025 / 7.085e6 = 286 µH
Primary peak: I_p,peak = √(2 · P_in / (L_p · f_sw)) = √(2 · 54.5 / (286e-6 · 65e3)) = √(109 / 18.59) = √5.86 = 2.42 A.
Secondary peak: I_s,peak = n · I_p,peak = 3.6 · 2.42 = 8.71 A.
Output cap sees I_s,peak − I_out_avg = 8.71 − 2 = 6.71 A of pulsing current → ripple current rating critical. Use polymer aluminum (e.g., Panasonic OS-CON or KEMET T520) at 1000 µF / 35 V with ≥ 3 A ripple rating, or 4 × 22 µF X7R ceramic in parallel.
MOSFET: 650 V super-junction (Infineon IPP60R125P6, 125 mΩ, V_DS = 650 V) with primary-side snubber (RCD clamp, typically 33 nF + 47 kΩ + UF4007) to absorb leakage-inductance spike.
Secondary rectifier: Schottky for V_R < 100 V (here V_R,peak = V_out + V_in,max/n = 24 + 375/3.6 ≈ 128 V → Schottky tight, use a 150 V part like PMEG10100E, or a Si fast-recovery STPS20H100). Synchronous rectification (a low-R_DS(on) MOSFET in place of the diode, driven by self-driven or controller-driven gate) recovers another 1.5–2 % efficiency at 24 V output but adds complexity.
Forward, push-pull, half-bridge, full-bridge
Transformer-coupled topologies where the transformer is operated bidirectionally (push-pull, bridge) or with a separate reset mechanism (forward). Voltage gain has the form V_out = D · V_in · (N_s / N_p), with effective D limited:
- Forward: D ≤ 0.5 (must reset core); add reset winding or active-clamp reset for D up to 0.7.
- Push-pull: D_eff per switch up to 0.5; combined output is full sine.
- Half-bridge: D up to 0.5 per switch, V across transformer is ±V_in/2.
- Full-bridge: V across transformer is ±V_in; effective D up to ~0.95.
LLC resonant converter
Half-bridge or full-bridge primary drives a series L_r–C_r–L_m resonant tank; secondary is a center-tapped or full-bridge rectifier. Output voltage is regulated by frequency, not duty (D = 0.5 fixed). ZVS on primary switches across the full load range, ZCS on secondary rectifiers — both gives 96–98 % efficiency and very low EMI. The standard architecture for premium server PSUs, fast chargers (USB-PD ≥ 100 W), and LED drivers.
Resonant frequency f_r = 1 / (2π · √(L_r · C_r)). Operating range: f_min < f_sw < f_max, both straddling f_r.
First-Harmonic Approximation (FHA) model: tank gain is
M(f_n, Q, L_n) = | (L_n · f_n²) / [(L_n + 1)·f_n² − 1) + j·Q·(f_n² − 1)·f_n·L_n] |
with f_n = f_sw / f_r, L_n = L_m / L_r, Q = √(L_r/C_r) / R_ac. Tune for unity-gain at the nominal operating point and gain > 1 / gain < 1 at the extreme line/load corners.
Three-phase inverter (SVPWM)
Six switches arranged as three half-bridges (A, B, C legs), each leg driven complementarily (with deadtime). The eight possible switch states give eight voltage vectors: 6 active (V₁–V₆ at 60° apart, magnitude (2/3)V_dc), and 2 zero (V₀, V₇).
Space-Vector PWM (SVPWM) synthesizes any reference vector V_ref in the αβ plane by time-averaging two adjacent active vectors and the zero vector within each PWM period. Maximum phase voltage (linear range, no overmodulation):
V_phase,peak = V_dc / √3 (vs V_dc/2 for simple sine-PWM)
SVPWM gives 15 % more output voltage than sine-PWM for the same DC bus, which is why every modern motor drive uses it.
Power factor correction (PFC)
Active PFC is almost always a boost converter placed between the bridge rectifier and the bulk DC capacitor. The control loop simultaneously regulates output voltage and shapes input current to follow input voltage:
i_in,ref(t) = G · |v_in(t)| → i_L follows |v_in| → pf → 1
Regulatory threshold: any offline supply > 75 W must meet EN 61000-3-2 (Class D harmonic limits), which forces pf ≥ ~0.95 in practice.
Worked example 3 — 5 kW three-phase motor drive, efficiency budget
DC bus 540 V (from 400 V_AC three-phase rectifier). Load 5 kW. Inverter at 10 kHz, six 1200 V / 40 A SiC MOSFETs (e.g., Wolfspeed C3M0040120K, R_DS(on) = 40 mΩ at 25 °C, ~64 mΩ at 125 °C).
Load current per phase RMS at 0.85 pf: I_phase = 5000 / (√3 · 400 · 0.85) = 8.5 A_rms → I_peak = 12.0 A.
Conduction loss per device: each phase leg shares duty between hi/lo switches. Approximate I_RMS through each switch as I_phase / √2 = 6.0 A. P_cond = 6.0² · 0.064 = 2.3 W per device → 6 · 2.3 = 13.8 W total.
Switching loss: SiC at V_dc = 540 V, I = 12 A peak, t_r + t_f ≈ 30 ns. E_sw ≈ ½ · 540 · 12 · 30e-9 = 97 µJ per transition. At 10 kHz, 2 transitions/cycle: P_sw = 97 µJ · 2 · 10e3 = 1.94 W per device → 6 · 1.94 = 11.6 W total.
Body-diode / freewheel loss (reverse-recovery in SiC ≈ 30 % of MOSFET switching): ~ 3.5 W total.
Bus capacitor ESR loss: 5 mΩ ESR × 4 A_rms ripple² ≈ 0.08 W (negligible — but the capacitor must be rated for that ripple, see thermal).
Total inverter losses ≈ 29 W → inverter efficiency = 5000 / (5000 + 29) = 99.4 %.
For comparison, the motor itself (a 5 kW IE3-class IPM, see [[Engineering/electric-motors]]): copper loss ~110 W, iron loss ~70 W, mechanical loss ~30 W → motor efficiency ~95.9 %. Motor losses are 7× inverter losses — at this power level the motor dominates, which is why every modern traction system pours engineering into motor design before squeezing the last drop from the inverter.
4. Reference data
Topology selection by power level
| Range | Typical topologies | Notes |
|---|---|---|
| < 5 W | linear (low dropout, LDO), charge pump, simple buck | Linear OK if (V_in − V_out)·I_out < ~1 W; charge pump avoids inductor for tiny boards |
| 5–100 W | buck, boost, flyback (universal isolated), SEPIC | Flyback dominant for offline isolated up to 75 W |
| 100–500 W | forward, two-switch forward, half-bridge, LLC for premium η | LLC takes over above ~100 W where flyback gets bulky |
| 500–2000 W | full-bridge, LLC, phase-shift full-bridge (PSFB), dual-active-bridge (DAB) for bidirectional | DAB is the de-facto answer for bidirectional EV onboard charger |
| 2–50 kW | three-phase rectifier + three-phase inverter, interleaved boost PFC, Vienna rectifier, NPC three-level | Vienna for unidirectional grid-tie PFC; NPC for medium-voltage drives |
| > 50 kW | modular multi-level converter (MMC), cascaded H-bridge | MMC dominates HVDC and STATCOM > 1 MW |
Common controller ICs
| Family | Use | Example part |
|---|---|---|
| TI TPS54xxx | Synchronous buck, integrated FETs, 2–25 A | TPS54331 (3 A), TPS548A28 (40 A) |
| TI LM5xxx / LM2xxx | Buck/boost controllers (external FET) | LM5145 (75 V buck controller) |
| TI UCC256xx / UCC28xxx | LLC + PFC controllers | UCC256402 (digital LLC), UCC28180 (CrCM PFC) |
| Analog Devices LTC / LTM | Precision buck/boost, µModule (cap+L+IC) | LTC3895 (150 V buck), LTM4625 (5 A µModule) |
| STMicroelectronics L4985 / L6562 | PFC | L4985 (combo PFC + LLC) |
| Infineon IRS / 2EDF / 1EDN | Half-bridge gate drivers, isolated gate drivers | IRS2104 (HV half-bridge), 1EDN7550 (isolated 8 A) |
| Power Integrations TOPSwitch / InnoSwitch | Fully-integrated flyback (controller + HV MOSFET) | INN3679C (USB-PD 65 W) |
| Microchip dsPIC33EP / Renesas RX | Digital power MCU (PWM + ADC for full-digital control) | dsPIC33CK256MP506 (160 MHz, 250 ps PWM) |
Switch selection by V_DS class
| Bus voltage | Switch class | Examples |
|---|---|---|
| 12–24 V (battery, USB) | 30–40 V Si MOSFET | Infineon IPB200N15N3 (15 V), Vishay SiSS72DN (30 V) |
| 48 V (telecom, light-EV) | 80–100 V Si MOSFET | Infineon BSC093N15NS5 (100 V), TI CSD18510Q5B (40 V) |
| 200–400 V (offline, single-phase DC link) | 600–650 V super-junction Si, 650 V GaN, 650 V SiC | Infineon CoolMOS IPB60R060P7, GaN Systems GS66508T, ROHM SCT3060AL |
| 400–800 V (three-phase, EV 400 V bus) | 1200 V SiC MOSFET, 1200 V IGBT | Wolfspeed C3M0040120K, Infineon FF600R12ME4 |
| 800–1500 V (EV 800 V, solar string, traction) | 1200–1700 V SiC, 1700 V IGBT module | Wolfspeed CAB400M12XM3, Mitsubishi CM1200DC-34T |
| > 3.3 kV (HVDC, traction) | 3.3–6.5 kV IGBT modules, IGCTs | ABB 5SNA 1500E330305, Hitachi MBN1500FH33 |
Magnetics core materials
| Family | Typical use | Examples | Notes |
|---|---|---|---|
| MnZn ferrite | High-f transformers + inductors 25 kHz–1 MHz | TDK PC95 / 3C95 / 3C97, Hitachi Finemet ML91S (B_sat 0.4–0.5 T) | Low core loss at high f; B_sat falls with T |
| NiZn ferrite | Very high f > 1 MHz, common-mode chokes | Fair-Rite 43, 61, 75 | Higher resistivity, less eddy loss |
| Powdered iron | Inductors > 100 kHz, distributed gap | Micrometals −26, −52, −60 mix; Magnetics Kool Mµ (Sendust) | Soft saturation (graceful current rise); higher loss than ferrite |
| Nanocrystalline | High-power isolation transformers, CMC | Hitachi Finemet FT-3M, VAC Vitroperm 500F (B_sat ~1.2 T) | Lowest core loss + high B_sat; expensive |
| Amorphous | Solar PV inductors, EV chargers | Metglas 2605SA1 (B_sat 1.56 T) | Low loss, ribbon form — fragile |
| Silicon steel | Line-frequency transformers, big inductors | M-6 grain-oriented (0.27 mm lamination) | Cheap; high loss above 1 kHz |
| Permalloy / Mu-metal | Magnetic shielding, common-mode chokes | 78 % Ni-Fe | High µ_r (50 000+), low B_sat |
Capacitor families for power electronics
| Family | Use | ESR / ESL | Watch-outs |
|---|---|---|---|
| Ceramic MLCC (X7R, X5R) | Output filter, decoupling, snubber | ~1 mΩ / ~1 nH (small package) | Massive DC-bias derating — X7R 0805 22 µF can drop to 4 µF at 5 V; mechanical microphonics |
| Polymer aluminum | Output bulk, low-ESR | 5–20 mΩ / 5 nH | Long life, no dryout; ripple current 1–5 A typical |
| Wet aluminum electrolytic | Bulk + DC link, high-V | 50–500 mΩ / 10–30 nH | Dries out with temperature; 10 °C halves life (Arrhenius); ESR rises with age |
| Film polypropylene | DC-link in inverters > 1 kW, snubbers, AC filtering | 1–5 mΩ / 5–50 nH | Excellent ripple capability + self-healing; bulky and expensive |
| Supercapacitor | Hold-up, energy buffer | High ESR (100s mΩ) | Energy density 1000× electrolytic but slow |
Typical efficiencies — what’s achievable
| Converter | Typical | Best in class | Notes |
|---|---|---|---|
| Linear regulator (LDO) | V_out / V_in × 100 % | — | 3.3 V from 5 V = 66 % max |
| Synchronous buck, 50 W | 85–93 % | ~95 % | GaN at high f hits 96+ % |
| Flyback, 30 W offline | 80–86 % | 88 % | Quasi-resonant or active-clamp |
| LLC, 500 W | 95–96 % | 97 % | Standard for server PSU bronze/silver |
| Server PSU, 1 kW | 91 % bronze, 94 % silver, 95.5 % gold, 96 % platinum, 96 %+ titanium | 97.5 % at 50 % load | 80 PLUS specification |
| Three-phase inverter, 5 kW | 96–98 % | 99 %+ (SiC) | GaN/SiC at low f_sw approaches 99.5 % |
| HVDC converter station, MMC | 98.5 % per station | 99 % | ABB / Siemens / GE state-of-art |
Cooling thresholds (rule of thumb)
| Power dissipation | Cooling | Hardware |
|---|---|---|
| < 1 W | PCB copper only | Small surface-mount package (SOT-23, SO-8) |
| 1–5 W | Natural convection on small heatsink or thermal-pad PCB | TO-220, D-PAK with copper pour |
| 5–30 W | Larger heatsink, natural convection | TO-247, D²PAK, vertical-mount heatsink |
| 30–100 W | Forced air | Heatsink + fan, ~10 °C/W → ~2 °C/W |
| 100–500 W | Forced air + large heatsink | Fan-cooled tower, 0.3–1 °C/W |
| 500 W–5 kW | Cold plate (water-glycol) | Direct-on-IGBT-module cold plate, 0.05–0.2 °C/W |
| > 5 kW | Two-phase / boiling, jet impingement, microchannel | Aerospace + EV traction |
Standard rails
| Rail | Use |
|---|---|
| 0.7–1.0 V | Modern CPU/SoC core (Ice Lake 0.9 V, Apple M-series ~0.7 V) |
| 1.0–1.1 V | DDR5 VDDQ (1.1 V), LPDDR5 |
| 1.2 V | DDR4 VDDQ, FPGA core (Xilinx UltraScale+ 0.85–0.97 V) |
| 1.8 V | DDR3 (legacy), I/O on most MCUs |
| 2.5 V | DDR3L, analog I/O |
| 3.3 V | Mainstream digital I/O, MCU supply |
| 5 V | USB, legacy logic |
| 12 V | Disk drives (legacy), automotive, server motherboards |
| 24 V | Industrial automation (PLC, sensor power, Ethernet/IP) |
| 48 V | Telecom (−48 V), datacenter 48 V rack bus, mild-hybrid EV |
| 200–400 V | Single-phase rectified DC link |
| 540–800 V | Three-phase rectified DC link, EV 400 V / 800 V class |
| ±2.5 kV–±800 kV | HVDC transmission |
5p. Theory — averaged modeling and small-signal control
A switching converter is a non-linear time-varying system. To design feedback for it we throw away the switching detail and replace the switch + diode with their cycle-averaged behavior. The classic technique is state-space averaging (Middlebrook + Ćuk, 1976): write the state equations for the ON and OFF subintervals, time-average them weighted by D and (1−D), then perturb around the operating point.
For a buck converter with state x = [i_L, v_C]ᵀ:
ON: ẋ = A_on · x + B_on · v_in OFF: ẋ = A_off · x + B_off · v_in
Averaged: ẋ = [D·A_on + (1−D)·A_off] · x + [D·B_on + (1−D)·B_off] · v_in.
Linearizing around (X, D, V_in) by writing d = D + d̂, x = X + x̂ gives the small-signal model:
x̂̇ = A · x̂ + B_d · d̂ + B_v · v̂_in
For voltage-mode buck CCM, the control-to-output transfer function G_vd(s) = v̂_out / d̂ is a double-pole at ω_0 = 1/√(LC), with a zero from ESR of C_out at ω_z = 1/(ESR·C):
G_vd(s) = V_in · (1 + s·ESR·C) / (1 + s·L/R + s²·LC)
Current-Mode Control (CMC) — the inner loop regulates inductor peak current directly. Effect: turns the double-pole into a single pole, drastically improves transient response, and inherently limits switch current cycle-by-cycle (overcurrent protection for free). Adds a sample-and-hold pole at f_sw/2 and a subharmonic instability if D > 0.5 — fixed by slope compensation.
Right-half-plane zero in boost and buck-boost. When the boost duty increases to demand more output power, the switch is ON longer → less of the cycle is spent transferring energy to the output → output voltage initially drops before it rises. This non-minimum-phase behavior gives an RHP zero in G_vd(s) at:
ω_RHPZ = R_load · (1 − D)² / L
You cannot push loop bandwidth past ~⅓ of ω_RHPZ without instability. Engineering response: keep L small, keep D small, or use an active-clamp / two-stage approach to avoid the problem.
Compensation networks. For voltage-mode buck with a double-pole + ESR zero you typically need Type III (two zeros, three poles) to get adequate phase margin at crossover. For current-mode with its single pole, Type II (one zero, two poles) suffices. Practical loop targets: crossover at ~ f_sw/10, phase margin ≥ 45°, gain margin ≥ 10 dB. Tools below automate this calculation.
Resonant converter analysis is done with the First-Harmonic Approximation (FHA): assume the square-wave drive into the resonant tank produces a near-sinusoidal current (true near resonance), replace the rectified load with an equivalent AC resistance R_ac = (8/π²) · R_load, and solve the tank as a frequency-dependent voltage divider. FHA gets gain and ZVS boundaries right to about 5 % near resonance; far from resonance you need full state-space or time-domain simulation.
6p. Application
Battery management
Cell balancer: small buck or buck-boost (or simply a series resistor switched on the most-charged cell) moves charge between adjacent cells in a stack. Active balancing (DC/DC between cells) recovers 90 %+ of the energy; passive (resistive shunt) burns it. Multi-cell CC/CV charger: constant-current until V_cell hits the regulation point (4.2 V for Li-ion, 3.65 V for LiFePO4), then constant-voltage with declining current until I < C/20 (end-of-charge). Implemented as a synchronous buck with current sense and dual-loop control (current loop inside, voltage loop outside, with smooth handoff).
Offline AC/DC supply (laptop adapter, server PSU)
Topology cascade:
- EMI filter — common-mode choke + X/Y caps to meet CISPR 22/32.
- Bridge rectifier — 4 diodes (or 4 MOSFETs for synchronous bridgeless PFC).
- Boost PFC — interleaved at higher power, CrCM at lower power; output 380–400 V DC nominal.
- Isolated DC/DC — LLC half-bridge (premium) or active-clamp flyback (compact / mid-power). Output 12–24 V.
- Synchronous secondary rectification + post-regulators (point-of-load buck) on the load board.
A modern 100 W USB-PD GaN charger collapses (3) + (4) into a single stage (quasi-resonant flyback with GaN) and runs at 200–500 kHz to shrink the transformer.
Motor drives
Three-phase inverter feeding an induction or PMSM motor (see [[Engineering/electric-motors]]). Switching frequency 2–20 kHz for industrial Si-IGBT drives, 10–30 kHz for SiC traction inverters, up to 100 kHz for compact GaN servo drives. Control: scalar V/Hz (HVAC pumps + fans), or Field-Oriented Control (FOC) with park/clarke transforms for high-performance servo + traction. Current sense via shunt + isolated amplifier or in-leg Hall (LEM LTSR), bus voltage sense via resistor divider + ADC. Encoder feedback for position, or sensorless flux observer for cost-down.
Solar inverter
- String inverter — 5–100 kW per unit, DC-side 600–1500 V from a series-parallel PV string, three-phase output to grid. MPPT (Maximum Power Point Tracking) algorithm modulates the DC-DC stage to keep the panel at its peak power point as irradiance + temperature change.
- Microinverter — 250–700 W per panel, single-phase or split-phase. Higher cost per watt but harvests more energy under shading (no string-level mismatch) and eliminates the dangerous 1000 V_DC roof wiring.
- Power optimizer + central inverter (SolarEdge architecture) — per-panel DC-DC + a single inverter, intermediate path.
Grid-tie inverters must comply with IEEE 1547 (US) / IEC 61727 + IEC 62116 for anti-islanding, ride-through, and grid-support functions (volt-var, frequency-watt).
EV traction inverter
DC bus from a 400 V or 800 V battery pack (Hyundai E-GMP, Porsche Taycan, GM Ultium are 800 V; most others including Tesla pre-2024 are 400 V class). Power 100–400 kW peak. Three-phase SiC MOSFET inverter at 10–30 kHz, liquid cooled, with insulation coordination + corona-onset margin (PD inception > 1.5× bus voltage). The main pain points are not topology — they are (a) thermal management of 99 %-efficient inverters dissipating only 1–4 kW but in a very small package, (b) partial-discharge-free insulation of the cooling-plate-to-power-module isolation (~6 kV impulse), and (c) common-mode bearing currents in the motor caused by inverter dv/dt (mitigated with dv/dt filters or insulated bearings).
Wireless power transfer
Series-parallel-tuned LC tank on the primary (transmit coil) driven by a half-bridge inverter at the resonant frequency, magnetically coupled (k = 0.1–0.5) to a secondary tank + rectifier. Qi standard (≤ 15 W phones) operates at 110–205 kHz; Ki cooking at 6.78 MHz ISM; automotive WPT3 (≥ 11 kW EV charging) at 79–90 kHz. Efficiency 75–92 % depending on coupling factor and alignment.
GaN-specific applications
GaN HEMTs (typically 100 V, 200 V, 650 V) have ~10× lower switching loss than equivalent-voltage Si MOSFETs and no body-diode reverse-recovery charge. That enables:
- USB-PD chargers (Anker, RAVPower, Apple): 65–240 W flyback or quasi-resonant active-clamp at 300–500 kHz → 50–70 % volume reduction.
- LiDAR laser pulse drivers: GaN’s sub-nanosecond switching delivers 100 A pulses into a laser diode in < 2 ns, enabling time-of-flight resolution to centimeters.
- High-frequency wireless charging (6.78 MHz Ki, 13.56 MHz custom).
- Automotive 48-V mild-hybrid and 800-V onboard chargers — GaN’s high-temperature operation + small size matter under the hood.
7p. Edge cases & assumptions
- CCM ↔ DCM boundary. Voltage gain, dynamics, and even sign-of-loop-gain change between modes. A converter that operates over 5 % to 100 % load must be designed in both modes, with a compensator that’s stable in both. The pragmatic answer is often forced CCM (synchronous rectifier replaces diode, so the inductor current can go negative and stay in CCM at light load) — at the cost of light-load efficiency and some EMI.
- Synchronous-rectifier dead-time. The two complementary switches in a half-bridge must not be on simultaneously — that’s shoot-through, putting V_bus directly across both R_DS(on) values, instantly destroying both. So you insert a dead-time (~20–100 ns) where both are off and the body diode of the synchronous device conducts. Too long a dead-time = excessive body-diode conduction (losses + reverse-recovery noise); too short = shoot-through risk. Adaptive dead-time controllers (TI UCD3138, dsPIC33CK) tune the dead-time per-cycle by monitoring SW-node behavior.
- dv/dt and di/dt-induced EMI. A SiC MOSFET turning off in 20 ns puts 25 V/ns onto the switch node. That couples through parasitic C_DS-to-PCB capacitance and through transformer interwinding capacitance into the ground plane → conducted common-mode noise at every harmonic of f_sw, from 150 kHz up past 30 MHz. Mitigations: gate-resistor slowdown (trades efficiency for EMI), gate-source ferrite bead, Faraday shield in transformer, Y-capacitor between primary and secondary (gives the common-mode current a low-impedance return path that bypasses the load), shielded layout.
- Common-mode noise in flyback. The biggest single source in offline supplies. Transformer interwinding capacitance (~50–500 pF) connects the switch node directly to the secondary ground. Mitigation: Faraday shield (a single foil layer between primary and secondary, grounded back to primary return), or cancellation winding (an auxiliary winding driven antiphase to cancel the displacement current).
- Capacitor aging. Wet aluminum electrolytics dry out; their ESR rises 2–4× over rated life. Life = L_0 · 2^((T_rated − T_actual)/10) — 10 °C cooler = 2× life. A 5000-hour 105 °C cap at 85 °C ambient lasts 20 000 h. Plan for output ripple to double over service life if you’ve used wet aluminum on the output.
- Magnetic saturation. The peak instantaneous current (not RMS, not average) must stay below the saturation point of the inductor or transformer. Once B exceeds B_sat the differential µ_r collapses → L drops by ~5–10× → di/dt explodes → switch sees a current step it can’t survive. Always check I_L,peak against the inductor’s I_sat in the datasheet — and reduce I_sat at hot operating temperature (some datasheets only quote 25 °C I_sat; ferrite I_sat falls 30 % to 125 °C).
- Loop bandwidth vs phase margin. Push loop crossover above f_sw/10 and the sampling effects of PWM start dominating; you’ll get glitches and limit cycles. Below f_sw/20 the converter responds slowly to load transients (and you need bigger output caps to compensate). Target: f_c = f_sw/10, ϕ_m = 45–60°, GM ≥ 10 dB.
- GaN gate sensitivity. GaN HEMTs typically have V_GS,max of only 6–7 V (vs Si MOSFET 15–20 V). A 30 ns ringing overshoot on a 5 V drive easily punches through. Dedicated GaN gate drivers (TI LMG1210, Silicon Labs Si827x) clamp the gate tightly and slow only the turn-on edge. Layout discipline (loop area, common-source inductance) is non-negotiable.
- SiC gate drive requires negative bias. Si MOSFETs are reliably OFF at V_GS = 0 V; SiC MOSFETs have a much lower V_GS(th) (typ 2 V) and large Miller capacitance, so during a fast V_DS rise the displacement current through C_GD pulls the gate above V_GS(th) → false turn-on → shoot-through. The fix: drive the gate to a negative voltage in the OFF state (typically −3 to −5 V), often using an isolated dual-rail bias supply (e.g., Murata MGJ2-series).
- Inrush. When an offline supply is first plugged in, the bulk capacitor is empty and looks like a short circuit. Peak inrush of 50–200 A flows through the bridge rectifier — must be limited with NTC thermistor (cheap, thermal latency), active inrush limiter (precharge resistor with bypass relay), or controlled-soft-start in the rectifier.
8p. Tools & software
Simulation
- LTspice (Analog Devices, free) — the industry standard for power-electronics simulation. Excellent library of switching FETs, IGBTs, and pre-built reference circuits from ADI / Linear Technology. Free, fast, and the SPICE engine handles the discontinuities of switching reasonably well.
- PLECS (Plexim) — block-diagram-style simulator that abstracts switches as ideal switches (no continuous SPICE-level transition); simulates large systems (full traction inverter + motor + load) in seconds where LTspice would take hours. Standard for control-loop design + system-level verification. Has an HIL counterpart (PLECS RT Box).
- PSIM (Powersim) — similar to PLECS, popular in academia + Asian power-electronics industry; tighter motor-drive modeling.
- MATLAB Simulink + Simscape Power Systems / Simscape Electrical — for control engineers already in the MATLAB ecosystem; integrates with Stateflow for digital control; full HIL toolchain (Speedgoat real-time targets).
- PSpice (Cadence) — solid, but expensive; mainly used in IC-design flow.
- SIMetrix / SIMPLIS — SIMPLIS is the piecewise-linear engine SIMetrix bundles; converges where SPICE chokes on switching transients.
- Saber (Synopsys) — automotive + aerospace heritage; pairs with VHDL-AMS / Verilog-A.
Magnetics design
- Coilcraft Designer / Würth REDEXPERT / TDK Design Tool — vendor selectors that input ripple-current spec and return suitable parts, including loss estimates.
- Magnetics Inc. Core Selector + their Inductor Design Tool — for custom-wound powder-iron / ferrite designs.
- MagNet / Infolytica (Siemens) — FEA for custom magnetic design.
- JMAG (JSOL Corp.) — FEA dominant in Japanese motor + transformer design houses.
- Ansys Maxwell — Western counterpart to JMAG; integrates with Simplorer for system simulation.
- MotorSolve / MotorXP — focused on rotating machines but useful for laminated magnetics.
Thermal
- 6SigmaET (Future Facilities) — purpose-built electronics thermal CFD.
- Mentor FloTHERM / Siemens Simcenter FLOEFD — industry standard for chassis-level CFD.
- Ansys Icepak — same niche; tighter integration with Ansys electromagnetic + mechanical.
- COMSOL Multiphysics — multi-domain (electro-thermal-mechanical) but slow on big boards.
- Reference-only manual calcs: junction-to-case from datasheet, board spreader from Cu thickness, sink from manufacturer θ_HA, sum the chain.
PCB-aware power layout
- Altium PDN Analyzer — DC-IR drop, current-density, plane-impedance analysis inside Altium.
- Cadence Sigrity Power Aware — same niche in the Cadence Allegro flow; adds AC PDN analysis.
- Hyperlynx PowerScope / PI (Siemens) — high-end PDN signoff.
- Keysight ADS — full-wave 3D for switch-node parasitics and EMI.
Vendor design tools
- TI Power Designer (free web tool) — schematic + BOM generation for TI parts, with PSPICE simulation behind it.
- Analog Devices LTpowerCAD — generates a fully-compensated buck/boost design from spec; computes loop, losses, BOM.
- Power Integrations PI Expert — flyback/forward design with their TOPSwitch/InnoSwitch parts; includes magnetics + thermal.
- Infineon iPosim — power-stage simulation with Infineon IGBT modules; loss + thermal for motor drives.
- Wolfspeed PowerEstimator + Microsemi MPLAB Mindi — SiC-specific.
- Magnetics Inc. AT Aircore Inductor Design Tool.
Open-source
- ngspice + KiCad’s ngspice integration — schematic-driven SPICE; weaker library than LTspice but usable.
- Qucs / QucsStudio — open SPICE front-end; supports Verilog-A.
- GeckoCIRCUITS (ETH Zurich) — academic power-electronics simulator; freeware.
- OpenModelica + Modelica Standard Library — multi-domain, modeler-friendly.
11. Cross-references
[[Engineering/semiconductor-devices]]— the switches inside every converter (MOSFET, IGBT, SiC, GaN, diode)[[Engineering/electric-motors]]— the dominant high-power load for inverters[[Engineering/transformers-power-systems]]— flyback / forward / LLC isolation transformers + the grid the converter ties to[[Engineering/electromagnetics-engineering]]— EMI generation + mitigation + inductor design[[Engineering/ac-analysis-three-phase]]— three-phase analysis + grid-tie inverter math[[Engineering/circuit-analysis]]— small-signal modeling foundation[[Engineering/op-amps]]— error amplifiers, current-sense amplifiers, compensation network design[[Engineering/digital-logic]]— gate drivers + protection logic + PWM generation[[Engineering/microcontrollers]]— digital power control (dsPIC, RX, C2000 MCUs)[[Engineering/classical-control]]— Type II / Type III compensator design, Bode-plot loop shaping[[Engineering/heat-transfer]]— cooling design, junction-to-ambient thermal resistance chains[[Engineering/pcb-design]]— switch-node + gate-loop layout for low parasitics + EMI control[[Robotics/power-systems]]— battery-to-motor-drive path on mobile robots[[Languages/Tier3/energy-power]]— grid + EV charging DSLs (OCPP, IEC 61850 GOOSE/MMS, SunSpec Modbus)
12. Citations
- Mohan, Undeland, Robbins. Power Electronics: Converters, Applications, and Design, 3rd ed., Wiley 2003. The canonical undergraduate text.
- Erickson, R. W. and Maksimović, D. Fundamentals of Power Electronics, 3rd ed., Springer 2020. The rigorous graduate text; state-space averaging, current-mode control, resonant converters.
- Pressman, A. I., Billings, K., Morey, T. Switching Power Supply Design, 3rd ed., McGraw-Hill 2009. Hands-on practitioner reference; magnetics worked examples.
- Kazimierczuk, M. K. Pulse-Width Modulated DC-DC Power Converters, 2nd ed., Wiley 2015. Deep treatment of CCM/DCM equations.
- Maksimović, D. and Zane, R. “Modeling, Analysis, and Control of Power Electronic Converters.” IEEE chapter.
- Kassakian, J. G., Schlecht, M. F., Verghese, G. C. Principles of Power Electronics, MIT/Addison-Wesley 1991. Still the cleanest derivation of averaged models.
- Texas Instruments application notes: SLUA series (PFC + LLC + flyback), SLVA series (DC/DC). Particularly SLUA561 (LLC design), SLUA779 (active-clamp flyback).
- Infineon Application Notes AN2007-04 (SiC), AN2010-04 (CoolMOS), AN2014-15 (resonant LLC).
- Analog Devices AN-1135 (LTspice for power supplies); LTpowerCAD documentation.
- Wolfspeed application notes: CPWR-AN30 (SiC drive), CPWR-AN02 (loss model).
- IEC 62477-1:2022 — Safety of power electronic converter systems and equipment (general).
- IEC 61800-3:2017 — Adjustable speed electrical power drive systems — Part 3: EMC requirements.
- CISPR 22:2008 / CISPR 32:2015 — Information technology equipment EMC limits + multimedia equipment.
- IEC 61000-3-2:2018 — Low-voltage harmonic current emissions limits.
- IEEE 519-2022 — Recommended Practice and Requirements for Harmonic Control in Electric Power Systems.
- UL 62368-1, 3rd ed., 2019 — Audio/video, information, and communication technology equipment safety (replaces UL 60950 + UL 60065).
- 80 PLUS specification (CLEAResult / Ecova) — server PSU efficiency tiers Bronze/Silver/Gold/Platinum/Titanium.
- IEEE 1547-2018 — Standard for Interconnection and Interoperability of Distributed Energy Resources.