Semiconductor Devices
See also (Tier 3 family index): Semiconductor Materials
1. At a glance
Semiconductor devices are the active elements of every electronic circuit — the building blocks that do something (rectify, switch, amplify, regulate) rather than merely store or dissipate energy as passive R, L, C components do. Four device families dominate practical engineering:
- pn-junction diodes — one-way valves for current. Rectification (AC to DC), reverse-voltage clamps, freewheel paths around inductive loads, voltage references (Zener), high-frequency switching, light emission (LED), and photodetection (photodiode). Schottky variants trade a higher reverse leakage for a lower forward drop and faster recovery.
- Bipolar Junction Transistors (BJT, NPN and PNP) — current-controlled amplifiers and switches. Two pn junctions back-to-back. Workhorse of analog amplifier and discrete current-source design from the 1950s through the 1980s, and still chosen today where transconductance per area, low input-referred noise, or precise V_BE matching matters (audio front-ends, bandgap references, sigma-delta ADCs).
- MOSFETs (NMOS and PMOS, enhancement and depletion modes) — voltage-controlled switches and amplifiers. A capacitor (gate) that inverts the channel underneath when a threshold voltage is exceeded. Dominant in digital (every CMOS gate is a paired NMOS+PMOS), in low-to-medium-power switching (synchronous buck/boost converters, motor controllers up to a few kW), and in modern analog IC design.
- IGBTs (Insulated-Gate Bipolar Transistors) — a MOSFET gate driving a bipolar output stage. High input impedance like a MOSFET, low conduction drop like a BJT. The default choice for motor drives, traction inverters, induction heating, and grid-tied converters from roughly 600 V to 6.5 kV and from tens of amps to several kiloamps per module.
Each device is characterised by a static (DC) operating region and a dynamic (switching) transition between regions. Reading the static curves tells you bias points, voltage drops, and quiescent power. Reading the switching curves tells you energy lost per transition, EMI generation, and how hot the part gets at a given switching frequency. Both views are needed for any design that runs longer than a textbook page.
Wide-bandgap materials — silicon carbide (SiC) and gallium nitride (GaN) — have moved from research curiosity to mainstream choice for high-voltage (≥600 V) and high-frequency (≥100 kHz) power conversion in the late 2010s and 2020s. They reduce switching losses by roughly an order of magnitude over silicon but demand more careful gate-drive layout, dV/dt and dI/dt management, and PCB current-loop control.
2. First principles
Semiconductors. A semiconductor is a crystal whose conductivity sits between an insulator and a metal and can be modulated by doping, electric field, light, or temperature. The defining parameter is the bandgap E_g — the energy a valence electron must absorb to become a free conduction-band electron, leaving a mobile hole in the valence band.
| Material | E_g at 300 K | Role |
|---|---|---|
| Germanium (Ge) | 0.66 eV | Historic, low V_F (~0.3 V); largely obsolete except in some RF and detector niches. |
| Silicon (Si) | 1.12 eV | Default for everything: diodes, BJTs, MOSFETs up to ~900 V, almost all logic and analog ICs. |
| Gallium arsenide (GaAs) | 1.42 eV | RF amplifiers (HEMT, MESFET), solar cells, laser diodes; direct-bandgap so it emits light efficiently. |
| Indium phosphide (InP) | 1.34 eV | Long-haul fibre-optic lasers and photodetectors. |
| Silicon carbide (SiC, 4H polytype) | 3.26 eV | High-voltage power devices (650 V – 6.5 kV) at high temperature (T_j up to 200 °C). |
| Gallium nitride (GaN) | 3.40 eV | Fast-switching power devices (100 V – 1.2 kV) and RF (5G, radar). |
| Diamond | 5.5 eV | Research-stage ultimate power semiconductor. |
A higher bandgap means a higher breakdown field (E_crit roughly proportional to E_g^{1.5}–E_g^2), which lets a thinner drift region hold off the same voltage. The thinner drift region has lower on-resistance and lower stored charge — hence the order-of-magnitude switching-loss reduction of SiC/GaN over Si at the same blocking voltage.
Doping. Pure (intrinsic) silicon has an electron concentration n_i ≈ 1.5 × 10¹⁰ /cm³ at 300 K — far too sparse to be useful. Doping substitutes a small fraction of silicon atoms with elements from group V (P, As, Sb — donors, contributing extra electrons → n-type) or group III (B, Al, Ga — acceptors, contributing holes → p-type). Typical doping concentrations range from 10¹⁵ /cm³ (lightly doped drift regions, ~10 Ω·cm resistivity) to 10²⁰ /cm³ (heavily doped contacts, ~0.001 Ω·cm).
The mass-action law n·p = n_i² holds at thermal equilibrium, so a 10¹⁷ /cm³ n-type region has p ≈ 2.25 × 10³ /cm³ — essentially no holes.
pn junction. When a p-region and an n-region meet, electrons diffuse from n to p and holes diffuse from p to n, leaving behind ionised dopant atoms. A depletion region (depleted of mobile carriers) forms, with a built-in electric field that opposes further diffusion. The built-in potential at equilibrium is:
V_bi = V_T · ln(N_A · N_D / n_i²)
where V_T = kT/q ≈ 25.85 mV at 300 K is the thermal voltage, and N_A, N_D are acceptor and donor concentrations. For a typical Si junction (N_A = N_D = 10¹⁷ /cm³), V_bi ≈ 0.82 V. The familiar “0.7 V forward drop” is not V_bi — it is the forward bias needed to inject enough minority carriers across the junction to support a useful current (typically a few mA in a small-signal diode).
Shockley diode equation. Under forward bias V > 0, the current through an ideal pn junction is:
I = I_S · [exp(V / (n · V_T)) − 1]
- I_S is the saturation current (10⁻¹² to 10⁻¹⁵ A for small-signal Si diodes, ~10⁻⁶ A for a 1 A Si rectifier; doubles roughly every 10 °C).
- n is the ideality factor: 1.0 for ideal diffusion, drifting to 2.0 at low currents (recombination in the depletion region) and degrading further at high currents (series resistance, high-injection effects).
- For V ≫ V_T the −1 is negligible and I rises exponentially with V at ~60 mV/decade at 300 K (ln(10)·V_T = 59.6 mV).
In reverse bias (V < 0) the equation predicts I = −I_S, a tiny constant leakage. In practice generation in the depletion region adds an additional ~V^{1/2} term, and at sufficient reverse bias avalanche or Zener breakdown causes sharp current rise. Zener breakdown (heavy doping, < 5 V) and avalanche breakdown (lighter doping, > 6 V) are exploited in voltage-reference diodes.
BJT (Bipolar Junction Transistor). Three terminals — emitter (E), base (B), collector (C) — separated by two pn junctions arranged either NPN (electron-conducting, faster, more common) or PNP. Operating principle: a small base current modulates a large collector-to-emitter current.
Operating regions for an NPN with V_BE the base-emitter voltage and V_CE the collector-emitter voltage:
- Cutoff: V_BE < ~0.5 V. Both junctions reverse-biased. I_C ≈ 0 except for leakage I_CEO ~ nA.
- Forward active: V_BE ≈ 0.6–0.7 V (BE junction forward), V_CE > V_CE_sat ≈ 0.2 V (BC junction reverse). I_C = β · I_B = I_S · exp(V_BE/V_T). This is the amplifier region.
- Saturation: V_CE drops to ~0.2 V. Both junctions forward-biased. I_C is set by external circuit, not by β. This is the “switch closed” region.
- Reverse active: swap collector and emitter; β is much lower (β_R ~ 1–5). Rarely useful.
The current gain β = I_C / I_B (also called h_FE on datasheets) ranges from 50 to 500 in typical small-signal devices, drops sharply at high I_C (high-injection), and varies ±30 % unit-to-unit even within a single part-number bin.
MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Four terminals — gate (G), drain (D), source (S), and body/bulk (B), usually tied to source. A thin (~2–10 nm in modern logic, 50–100 nm in power devices) gate-oxide layer separates the gate metal from the channel region. Applying V_GS attracts (NMOS) or repels (PMOS) carriers under the oxide, forming or removing a conductive channel between source and drain.
Operating regions for an N-channel enhancement MOSFET:
- Cutoff (subthreshold): V_GS < V_th. Channel not formed. I_D ~ exp(V_GS/V_T) × very small prefactor; in modern logic this leakage matters.
- Triode (linear, ohmic): V_GS > V_th and V_DS < V_GS − V_th. I_D = μ_n · C_ox · (W/L) · [(V_GS − V_th)·V_DS − V_DS²/2]. The channel behaves like a voltage-controlled resistor; this is the “switch closed” region for power MOSFETs, where R_DS(on) ≈ 1 / [μ_n · C_ox · (W/L) · (V_GS − V_th)] characterises conduction loss.
- Saturation (active): V_DS ≥ V_GS − V_th. Channel pinches off at the drain end. I_D = ½ · μ_n · C_ox · (W/L) · (V_GS − V_th)² · (1 + λ·V_DS). The square-law amplifier region.
Threshold voltage V_th is 0.5–1.0 V for “logic-level” MOSFETs (fully on at 4.5 V), 2–4 V for “standard” MOSFETs (need 10 V to fully turn on), and 1.5–3 V for SiC MOSFETs.
IGBT (Insulated-Gate Bipolar Transistor). Cross-section is a MOSFET stacked on top of a PNP bipolar. The MOSFET gate controls the bipolar’s base, giving the device a high-impedance voltage input like a MOSFET and a low-V_CE(sat) conduction like a BJT. Used almost exclusively at V ≥ 600 V and I ≥ 10 A, where MOSFET R_DS(on) × area becomes prohibitive on silicon. SiC MOSFETs are eroding IGBTs from below (600–1700 V); IGBTs still dominate at 3.3 kV and above.
Drawbacks: a parasitic PNP gives the IGBT a “tail current” at turn-off (minority carriers must recombine), limiting practical switching frequency to ~10–30 kHz for Si IGBTs versus ~100 kHz – 1 MHz for Si MOSFETs.
3. Practical math / design equations
Diode forward drop (engineering values)
| Diode type | Forward drop V_F at rated current | Reverse recovery t_rr | Comment |
|---|---|---|---|
| Small-signal Si (1N4148) | 0.6–0.7 V at 10 mA | 4 ns | Logic signal switching, clamping. |
| Si rectifier (1N4001 – 1N4007) | 1.0–1.1 V at 1 A | ~30 µs | 50–1000 V mains rectification. |
| Schottky (1N5817 – 1N5822) | 0.35–0.55 V at 1–3 A | ~10 ns | Low-drop OR-ing, freewheel in low-V converters. |
| Ultrafast Si (UF4007, MUR series) | 1.0–1.3 V at 1 A | 35–75 ns | Freewheel in 100 kHz off-line converters. |
| SiC Schottky (C3D series) | 1.5–1.7 V at 10 A | ~0 (no minority storage) | 650–1700 V freewheel/boost; near-zero switching loss. |
| Germanium (1N34A) | 0.25–0.35 V at 5 mA | n/a | Largely historic; some RF detector use. |
Forward drop is negative-temperature-coefficient at constant current (~ −2 mV/°C for Si). This is why a forward-biased pn junction is a usable temperature sensor — and why paralleled diodes need ballast resistors to share current.
BJT large-signal model (forward-active)
- V_BE_on ≈ 0.7 V (Si small-signal at 1–10 mA); +60 mV per decade of I_C; −2 mV/°C at constant I_C.
- I_C = β · I_B = I_S · exp(V_BE / V_T). I_S ≈ 10⁻¹⁵ A for a 2N3904; doubles every 10 °C.
- V_CE_sat ≈ 0.2 V at I_C up to ~0.5·I_C(max); rises to 0.5–1.0 V near rated current.
- Early effect: I_C has a finite slope vs V_CE; extrapolation crosses V_CE axis at −V_A (Early voltage), typically 50–200 V for small-signal NPNs.
BJT small-signal (hybrid-π) model
Linearised about a quiescent operating point (I_CQ, V_CEQ):
- Transconductance: g_m = I_CQ / V_T (e.g. at I_CQ = 1 mA, g_m = 38.5 mS).
- Input resistance: r_π = β / g_m (e.g. β = 100, g_m = 38.5 mS → r_π = 2.6 kΩ).
- Output resistance: r_o = V_A / I_CQ (Early voltage ~100 V at I_CQ = 1 mA → r_o = 100 kΩ).
- Open-circuit voltage gain of a transistor alone (no external resistors): a_v = g_m · r_o = V_A / V_T ≈ 100 V / 25.85 mV ≈ 3870. The “intrinsic gain” of a BJT.
MOSFET large-signal saturation
I_D = ½ · μ_n · C_ox · (W/L) · (V_GS − V_th)² · (1 + λ·V_DS)
In practice you don’t measure μ_n·C_ox; you read I_D vs V_GS from the datasheet “transfer characteristics” curve.
MOSFET small-signal
- Transconductance: g_m = √(2 · μ_n · C_ox · (W/L) · I_D) = 2·I_D / (V_GS − V_th). Note: depends on √I_D (vs BJT’s linear I_C) — at the same bias current, a BJT has substantially higher g_m than a MOSFET.
- Output resistance: r_o = 1 / (λ · I_D). λ is set by channel length and is the analogue of 1/V_A; modern short-channel devices have poor r_o (low intrinsic gain).
MOSFET R_DS(on) and the “FOM” (figure of merit)
Switching MOSFETs are characterised by R_DS(on) × Q_g (mΩ × nC). Lower is better — it captures the trade between conduction loss (∝ R_DS(on)) and gate-drive switching loss (∝ Q_g · f_sw · V_drive). State-of-the-art silicon MOSFETs at 100 V achieve ~50 mΩ·nC; GaN devices at 100 V achieve ~5 mΩ·nC — a 10× improvement.
Switching energy (inductive load, hard switching)
For a MOSFET or IGBT switching a clamped inductive load (the dominant case in motor drives and DC-DC converters), turn-on and turn-off losses approximate to:
E_on ≈ ½ · V_DS,off · I_load · t_r E_off ≈ ½ · V_DS,off · I_load · t_f
Total switching loss at frequency f_sw:
P_sw = (E_on + E_off) · f_sw
Conduction loss in the on-state:
P_cond = I_load² · R_DS(on) · D (MOSFET) P_cond = V_CE,sat · I_load · D (IGBT)
where D is duty cycle.
Worked example 1 — BJT common-emitter amplifier
Design a CE amplifier with a 12 V supply, β = 100, target Q-point V_CEQ = 6 V, I_CQ = 2 mA, voltage-divider biased.
Choose R_C. I_CQ · R_C = V_CC − V_CEQ − I_EQ · R_E. Allocate ~1 V to emitter degeneration (R_E):
R_E ≈ 1 V / I_EQ ≈ 1 V / 2 mA = 500 Ω → pick 510 Ω (E24). R_C = (12 V − 6 V − 1.02 V) / 2 mA = 4.98 V / 2 mA = 2.49 kΩ → pick 2.4 kΩ (E24).
Recompute V_CEQ = 12 − 2 mA · (2.4 kΩ + 510 Ω) = 12 − 5.82 = 6.18 V. Close enough.
Bias divider R_1, R_2. Set base bias V_B = V_E + V_BE = (2 mA · 510 Ω) + 0.7 V = 1.02 + 0.7 = 1.72 V. To make the bias stiff against β variation, set divider current i_div ≈ 10·I_BQ = 10·(I_CQ/β) = 10·(20 µA) = 200 µA.
R_1 + R_2 = V_CC / i_div = 12 V / 0.2 mA = 60 kΩ. R_2 = V_B / i_div = 1.72 V / 0.2 mA = 8.6 kΩ → pick 8.2 kΩ (E24). R_1 = 60 − 8.2 = 51.8 kΩ → pick 51 kΩ (E24).
Small-signal gain (mid-band, R_E bypassed by capacitor C_E):
g_m = I_CQ / V_T = 2 mA / 25.85 mV = 77.4 mS. r_π = β / g_m = 100 / 77.4 mS = 1.29 kΩ.
Voltage gain (assuming R_L = ∞ at output and r_o ≫ R_C, both reasonable):
A_v = −g_m · R_C = −77.4 mS · 2400 Ω = −186 V/V (about 45 dB, inverted).
With R_E un-bypassed (no C_E): A_v ≈ −R_C / R_E = −2400/510 = −4.7 V/V. The bypass capacitor trades stability (which is a DC concern, set by R_E) for AC gain. C_E must reactance-short R_E at the lowest signal frequency: at f = 20 Hz, |1/(2πfC_E)| ≪ R_E means C_E ≫ 1/(2π·20·510) ≈ 15.6 µF → pick 100 µF.
Worked example 2 — MOSFET switching loss (IRF540N)
IRF540N driving a 12 V, 5 A inductive load at f_sw = 50 kHz with t_r = 50 ns, t_f = 60 ns, R_DS(on) = 44 mΩ (at V_GS = 10 V, T_j = 25 °C; rises to ~88 mΩ at T_j = 100 °C), duty cycle D = 0.5.
Conduction loss (hot, T_j = 100 °C):
P_cond = I² · R_DS(on) · D = (5 A)² · 88 mΩ · 0.5 = 25 · 0.088 · 0.5 = 1.10 W.
Switching loss:
E_on = ½ · V_DS · I · t_r = ½ · 12 V · 5 A · 50 ns = 1.50 µJ. E_off = ½ · V_DS · I · t_f = ½ · 12 V · 5 A · 60 ns = 1.80 µJ. P_sw = (E_on + E_off) · f_sw = 3.30 µJ · 50 kHz = 0.165 W.
Gate-drive loss (Q_g ≈ 71 nC from datasheet at V_GS = 10 V):
P_gate = Q_g · V_drive · f_sw = 71 nC · 10 V · 50 kHz = 35.5 mW. (Dissipated in gate driver and gate resistor, not in the MOSFET die itself.)
Total MOSFET die dissipation: 1.10 + 0.165 = 1.27 W. With a TO-220 package θ_JA ≈ 62 °C/W free air (or ~30 °C/W with a small clip-on heatsink), die temperature rise is 1.27 · 30 = 38 °C above ambient with the heatsink — well within limits at 25 °C ambient.
Observation: At 12 V, 5 A, 50 kHz, conduction loss dominates by ~7:1 over switching loss. Increase to 100 kHz and switching loss doubles, conduction unchanged — the crossover where switching loss matters more than R_DS(on). At 1 MHz, switching loss is 3.3 W and the IRF540N is the wrong device — switch to GaN or pick a MOSFET with lower Q_g (smaller die, higher R_DS(on), but better FOM).
Worked example 3 — Buck converter freewheel diode selection
A buck converter switches at f_sw = 100 kHz, V_in = 24 V, V_out = 12 V, I_load = 5 A. The freewheel diode conducts during the off-portion of each switching cycle (D_off = 1 − V_out/V_in = 0.5) and reverse-blocks 24 V during the on-portion.
Forward-conduction loss at I_F = 5 A, D_off = 0.5:
- Standard recovery 1N5408 (V_F ≈ 1.0 V, t_rr ≈ 2 µs): P_cond = 1.0 V · 5 A · 0.5 = 2.5 W. But at 100 kHz the period is 10 µs, and t_rr = 2 µs means the diode is still recovering for 20 % of each cycle — completely unusable. Reverse-recovery current spikes destroy the MOSFET.
- Ultrafast UF5408 (V_F ≈ 1.3 V, t_rr ≈ 75 ns): P_cond = 1.3 · 5 · 0.5 = 3.25 W; reverse-recovery energy E_rr ≈ ½ · V_R · Q_rr ≈ ½ · 24 V · 60 nC ≈ 0.72 µJ → P_rr at 100 kHz = 72 mW. Acceptable but the V_F costs efficiency.
- Schottky MBR1045 (V_F ≈ 0.55 V at 5 A, V_R = 45 V, no minority storage): P_cond = 0.55 · 5 · 0.5 = 1.38 W; effectively zero switching loss. Best choice — and the standard answer for buck converters below ~60 V.
- SiC Schottky C3D02060A (V_F ≈ 1.5 V at 5 A, V_R = 600 V, zero t_rr): wasteful here because V_F is too high, and the 600 V rating is gross overkill for a 24 V bus. SiC Schottky shines at V_R ≥ 200 V where Si Schottkys run out of voltage.
Conclusion: at V_in ≤ 40 V choose Schottky; at 40–200 V choose ultrafast Si (or use a synchronous MOSFET); at ≥ 200 V choose SiC Schottky or synchronous SiC MOSFET. The 1N400x family is mains-rectifier only — never put it in a switching converter.
4. Reference data
Diode families
| Part | Type | V_R (V) | I_F avg (A) | V_F typ | t_rr | Package | Notes |
|---|---|---|---|---|---|---|---|
| 1N4148 / 1N914 | Small-signal Si | 100 | 0.2 | 0.7 V @ 10 mA | 4 ns | DO-35 | Universal signal diode; through-hole. |
| LL4148, BAV99 | Small-signal Si SMD | 100 | 0.2 | 0.7 V @ 10 mA | 4 ns | SOD-80, SOT-23 | SMD signal-diode default. |
| 1N4001 – 1N4007 | Si rectifier | 50–1000 | 1 | 1.0 V @ 1 A | ~30 µs | DO-41 | Mains rectification. Not for switching. |
| 1N5817 – 1N5822 | Schottky | 20–40 | 1–3 | 0.45 V @ 1 A | 10 ns | DO-41 | Low-V power switching, freewheel. |
| SS14 / SS34 | Schottky SMD | 40 | 1–3 | 0.5 V @ 1 A | 10 ns | SMA, SMC | SMD low-V Schottky default. |
| MBR1045, MBR2045 | Schottky | 45 | 10/20 | 0.55–0.65 V | <50 ns | TO-220 | Buck/boost freewheel up to 40 V. |
| MUR460, UF4007 | Ultrafast Si | 600/1000 | 4/1 | 1.3 V | 35–75 ns | DO-201, DO-41 | Off-line PFC, flyback secondary. |
| C3D02060A, C3D10065A | SiC Schottky | 600 | 2–10 | 1.5 V | ~0 | TO-220, TO-247 | High-V PFC boost; zero t_rr. |
| C6D10120A | SiC Schottky | 1200 | 10 | 1.6 V | ~0 | TO-247 | Three-phase PFC, traction. |
| 1N5231B – 1N5267B | Zener (small) | n/a | 0.5 W | V_Z = 5.1 V–75 V | n/a | DO-35 | Reference and clamp. |
| TVS arrays (e.g. SMAJ, USBLC6) | Transient suppressor | various | brief pulse to kA | clamp | <1 ns | various | ESD/lightning protection. |
| LED (e.g. WS2812, OSRAM LR W5SM) | Light-emitting | n/a | 20 mA – 1 A | 1.8 V (red) to 3.4 V (blue/white) | n/a | various | I_F regulated by external current source. |
| Photodiode (BPW34, OSI PIN-10D) | Photo-detect | n/a | µA – mA | reverse biased | n/a | various | Operate at I_R ∝ light. |
BJT families
| Part | Type | V_CEO (V) | I_C max (A) | β (h_FE) | f_T (MHz) | Package | Typical price | Notes |
|---|---|---|---|---|---|---|---|---|
| 2N3904 | NPN small-signal | 40 | 0.2 | 100–300 | 300 | TO-92 | $0.05 | Through-hole jellybean. |
| 2N3906 | PNP small-signal | 40 | 0.2 | 100–300 | 250 | TO-92 | $0.05 | PNP companion to 2N3904. |
| BC547 / BC557 | NPN/PNP small-signal | 45 | 0.1 | 110–800 | 300 | TO-92 | $0.05 | European jellybean. |
| 2N2222A | NPN, medium | 40 | 0.8 | 100–300 | 300 | TO-18, TO-92 | $0.10 | Higher current than 2N3904. |
| 2N2907A | PNP, medium | 40 | 0.6 | 100–300 | 200 | TO-18, TO-92 | $0.10 | PNP companion. |
| MMBT3904, MMBT3906 | SMD versions | 40 | 0.2 | 100–300 | 300 | SOT-23 | $0.02 | SMD jellybean. |
| BC817, BC807 | NPN/PNP SMD | 45 | 0.5 | 100–600 | 100 | SOT-23 | $0.03 | Higher-current SOT-23. |
| TIP31, TIP32 | NPN/PNP medium-power | 40–100 | 3 | 25–50 | 3 | TO-220 | $0.40 | Older Darlington-driver workhorse. |
| TIP120, TIP125 | NPN/PNP Darlington | 60 | 5 | 1000+ | — | TO-220 | $0.50 | Two-stage gain; slow. |
| 2N3055 | NPN power | 60 | 15 | 20–70 | 0.8 | TO-3 | $1.00 | Classic linear-supply pass element. |
| MJE13007 | NPN switching | 400 | 8 | 8–40 | 14 | TO-220 | $0.50 | Off-line flyback (Si). |
| BFR93A, BFP540 | NPN RF | 12 | 0.05 | 60–250 | 5000–7000 | SOT-23, SOT-343 | $0.50 | RF amplifier front-end. |
| 2SC5200, 2SA1943 | NPN/PNP audio power | 230 | 15 | 55–160 | 30 | TO-3P | $5 | Audio power amp output stage. |
MOSFET families
| Part | Type | V_DS (V) | I_D (A) | R_DS(on) (mΩ) | Q_g (nC) | Package | Notes |
|---|---|---|---|---|---|---|---|
| 2N7000, BS170 | N-ch small-signal | 60 | 0.2 | 5000 (at V_GS = 10 V) | 5 | TO-92 | Logic-driver. |
| 2N7002 | N-ch small-signal SMD | 60 | 0.115 | 7500 | 5 | SOT-23 | SMD jellybean MOSFET. |
| BSS84 | P-ch small-signal SMD | −50 | −0.13 | 10000 | 5 | SOT-23 | High-side load switch logic. |
| IRLZ44N | N-ch logic-level | 55 | 47 | 28 (V_GS = 5 V), 22 (10 V) | 48 | TO-220 | ”5 V drive” hobby workhorse. |
| IRF540N | N-ch | 100 | 33 | 44 (V_GS = 10 V) | 71 | TO-220 | Classic 100 V workhorse. |
| IRF7416 | P-ch SO-8 | −30 | −10 | 20 (V_GS = −10 V) | 18 | SO-8 | Battery-pack high-side switch. |
| IRFP260N | N-ch | 200 | 50 | 40 | 245 | TO-247 | High-current 200 V. |
| IPP200N25N3 | N-ch CoolMOS | 250 | 64 | 19 | 53 | TO-220 | Infineon superjunction. |
| STP55NF06 | N-ch | 60 | 50 | 14 | 73 | TO-220 | Synchronous-rectifier on 48 V bus. |
| IPW65R019C7 | N-ch CoolMOS C7 | 650 | 75 | 19 | 116 | TO-247 | Off-line PFC / LLC. |
| GS66508T | GaN E-mode | 650 | 30 | 50 | 5.8 | GaNPX | MHz-class hard switching. |
| EPC2052 | GaN E-mode | 100 | 31 | 4.4 | 4 | LGA | High-frequency POL. |
| C2M0080120D | SiC MOSFET | 1200 | 36 | 80 | 91 | TO-247 | Wolfspeed gen-2 SiC. |
| C3M0065090D | SiC MOSFET gen-3 | 900 | 35 | 65 | 51 | TO-247 | Wolfspeed gen-3. |
| IPC100R070P7 | SiC MOSFET | 1000 | 25 | 70 | 30 | TO-247 | Infineon CoolSiC. |
IGBT families
| Part | V_CES (V) | I_C (A) | V_CE(sat) | E_off (mJ) | Package | Notes |
|---|---|---|---|---|---|---|
| IRGB4045D | 600 | 60 | 1.4 V @ 30 A | 1.0 | TO-247 | Co-packaged anti-parallel diode; motor drive. |
| IRGP4063D | 600 | 96 | 1.4 V @ 48 A | 2.1 | TO-247 | Higher-current motor inverter leg. |
| IKW40N120T2 | 1200 | 80 | 2.0 V @ 40 A | 2.0 | TO-247 | Industrial 480 V three-phase. |
| FGH60N60SMD | 600 | 120 | 1.95 V @ 60 A | — | TO-247 | Solar inverter. |
| FF600R12ME4 (module) | 1200 | 600 | 1.7 V @ 600 A | ~100 | EconoDUAL3 | Half-bridge module; 400 V mains motor drive. |
| FZ1200R65KE3 | 6500 | 1200 | 4.0 V @ 1200 A | ~2000 | IHM-B module | Traction (locomotive, MV drive). |
Generation labels (Infineon nomenclature): IGBT4 (introduced ~2007, 600/1200 V workhorses), IGBT5/7 (lower V_CE,sat, higher T_j up to 175 °C, faster switching). Each generation reduces total loss ~15–20 % vs the prior at the same blocking voltage.
Standard package thermal resistance (junction-to-ambient, no heatsink, free air)
| Package | θ_JA (°C/W) | θ_JC (°C/W) | Notes |
|---|---|---|---|
| SOT-23 | 250 | 75 | 1206-footprint signal MOSFET / BJT. |
| SO-8 | 100 | 30 | DIP-replacement power. |
| DPAK (TO-252) | 70 | 6 | SMD power, tab on solder. |
| D2PAK (TO-263) | 50 | 3 | Bigger DPAK. |
| TO-220 | 62 | 1.5 | Through-hole standard power; needs heatsink for >2 W. |
| TO-247 | 40 | 0.5 | Higher-power through-hole. |
| TO-3 | 35 | 1.5 | Metal-can classic. |
| TO-263-7 (D2PAK-7) | 35 | 0.8 | Modern surface-mount power. |
5p. Theory
Depletion-region physics
For a step pn junction with doping N_A (p side) and N_D (n side), the depletion-region width under bias V_R (reverse bias positive) is:
W = √(2·ε_s · (V_bi + V_R) / q · (1/N_A + 1/N_D))
where ε_s = 1.04 × 10⁻¹² F/cm for Si. The maximum electric field at the junction is:
E_max = √(2·q · (V_bi + V_R) · (N_A · N_D) / (ε_s · (N_A + N_D)))
Breakdown occurs when E_max reaches the critical field E_crit (≈ 3 × 10⁵ V/cm for Si, ≈ 3 × 10⁶ V/cm for SiC and GaN). This sets the R_DS(on) × area limit (“silicon limit”):
R_on · A ∝ V_BR^2.5 / (μ · ε_s · E_crit^3)
The factor of (E_crit_SiC / E_crit_Si)³ ≈ 1000 explains why SiC achieves 1/10 to 1/100 the on-resistance of Si at the same breakdown voltage — even before the higher μ × N_D product is counted.
MOSFET square-law vs short-channel
The square-law I_D = ½·μ·C_ox·(W/L)·(V_GS − V_th)² assumes constant carrier mobility from source to drain. In modern logic (channel length < 100 nm) and at high V_GS in power MOSFETs, the channel field exceeds the velocity-saturation field E_sat ≈ 1 × 10⁴ V/cm (Si), and carriers stop accelerating. The drain current then becomes approximately linear in (V_GS − V_th):
I_D ≈ W · C_ox · v_sat · (V_GS − V_th)
with v_sat ≈ 10⁷ cm/s in Si. For digital CMOS this means scaling V_dd lowers I_D less than the square-law would suggest — good for switching speed, bad for static power.
BJT Ebers-Moll model
A more complete BJT model than the forward-active approximation, valid across all four operating regions:
I_E = I_ES · [exp(V_BE/V_T) − 1] − α_R · I_CS · [exp(V_BC/V_T) − 1] I_C = α_F · I_ES · [exp(V_BE/V_T) − 1] − I_CS · [exp(V_BC/V_T) − 1]
where α_F = β_F / (β_F + 1) ≈ 0.99 (forward common-base gain) and α_R ≈ 0.5–0.9 (reverse). Saturation occurs when V_BC > 0 and both exponentials contribute — at that point the second term in the I_C equation subtracts substantially from the first and V_CE drops to V_CE_sat.
Junction capacitances
Every pn junction has two capacitance contributions:
- Depletion (junction) capacitance C_j = ε_s·A / W ∝ 1/√(V_bi + V_R) — dominates under reverse bias.
- Diffusion (charge-storage) capacitance C_d ∝ τ · I — dominates under forward bias, where τ is minority-carrier lifetime.
For BJTs:
- C_je (emitter-base junction) — small, ~5–50 pF in small-signal; sets f_T at low currents.
- C_jc (collector-base junction) — usually larger, ~1–10 pF; subject to Miller multiplication in common-emitter configurations: the apparent input capacitance is C_jc · (1 + A_v), which limits bandwidth in high-gain stages.
For MOSFETs:
- C_gs (gate-source) — bulk of the gate-drive charge in the linear region.
- C_gd (gate-drain) — small geometrically but dominant in switching because of the Miller plateau: during the V_DS transition, the gate-drive current is consumed pulling C_gd through ΔV_DS rather than charging C_gs. This holds V_GS constant at the threshold + (I_D / g_m) for the full duration of the V_DS swing, which sets t_r and t_f.
- C_ds (drain-source) — sets output capacitance; resonates with package and PCB inductance during switching transitions.
A common Miller-plateau calculation: a MOSFET with C_gd = 200 pF, switching V_DS from 12 V to 0, with a gate driver supplying 1 A through the gate resistor, takes Δt = C_gd · ΔV_DS / I_drive = 200 pF · 12 V / 1 A = 2.4 ns. This is the minimum switching time — actual t_f is typically 2–3× longer because of parasitic source inductance and Miller-plateau gate current limits.
Tellegen’s theorem applies to nonlinear circuits too
Tellegen’s theorem (introduced in [[Engineering/circuit-analysis]]) does not require linear element constitutive relations — only KCL and KVL. It therefore applies to networks with diodes, transistors, switches, and arbitrary nonlinear elements. The sum Σ v_k·i_k = 0 over all branches at every instant, which is conservation of power. This is the bookkeeping tool that lets you sanity-check a switching-converter simulation: power in must equal power out plus all losses, instant by instant.
6p. Application
Choosing between BJT and MOSFET
| Criterion | Favours BJT | Favours MOSFET |
|---|---|---|
| Drive impedance | Already-current-driven inputs (DAC outputs, photodiode currents) | Logic outputs (zero static drive current) |
| Input bias current | Tolerable (µA range) | Must be zero (∼pA gate leakage) |
| Transconductance per drive current | High (g_m = I_C / V_T) | Low (g_m = √(2β·I_D)) |
| Matched-pair accuracy | Excellent (V_BE tracks log(I_C) precisely) | Lower (V_th mismatch ±10 mV) |
| 1/f noise | Lower | Higher (surface-trapped charge in oxide) |
| On-resistance at high current | Saturates at 0.2–1 V — independent of I_C | Goes to zero linearly with W/L — better at low V, high I |
| Switching speed | Limited by charge storage | Faster (majority-carrier device) |
| Driver complexity | Base resistor only | Needs gate driver (especially high-side) |
| Power dissipation, linear regulator | Acceptable (V_CE,sat at edge) | Excellent (R_DS(on) → 0) |
| Power dissipation, switching | High (storage time, recovery) | Low |
Rule of thumb in 2026: for switching, MOSFETs above 100 mA and below 600 V (or up to 1700 V with SiC). For analog amplifier front-ends where matching, low noise, or large g_m matters, BJT or JFET. For linear pass elements above 10 W, MOSFET. For motor drives above 1 kW and 600 V, IGBT or SiC MOSFET.
Choosing between Si MOSFET, SiC MOSFET, and IGBT for power switching
| Voltage class | Frequency | Typical choice (2026) |
|---|---|---|
| ≤ 100 V | any | Si MOSFET, GaN above 200 kHz |
| 200–600 V | < 50 kHz | Si MOSFET (superjunction) or IGBT |
| 200–600 V | > 100 kHz | GaN or SiC MOSFET |
| 600–1700 V | < 30 kHz | Si IGBT (cheapest) |
| 600–1700 V | > 30 kHz | SiC MOSFET |
| 3.3–6.5 kV | any | Si IGBT (SiC available but expensive) |
Thermal design
Steady-state die temperature:
T_j = T_a + P_diss · (θ_JC + θ_CS + θ_SA)
where θ_CS is case-to-sink (with proper thermal grease and torque, 0.1–1.0 °C/W; with a poor mount, 5+ °C/W) and θ_SA is sink-to-ambient (heatsink characteristic). The maximum allowable T_j is 150 °C for ordinary Si parts, 175 °C for “industrial” Si, 200 °C for SiC MOSFETs (silicon limit of metallisation), and 600+ °C for SiC die alone (limited by packaging, not the semiconductor).
Junction-to-case dominates for high-power dissipation. A TO-247 IGBT module at θ_JC = 0.25 °C/W dissipating 100 W has 25 °C rise from die to case — already half the budget. Heatsink design must take the rest.
Safe Operating Area (SOA)
A datasheet “SOA” plot shows allowed I vs V_DS (MOSFET) or I_C vs V_CE (BJT/IGBT) for a given pulse length. There are three limits:
- Current limit (horizontal upper bound) — set by metallisation electromigration and wire-bond fusing.
- Voltage limit (vertical right bound) — set by breakdown.
- Thermal limit (diagonal in log-log) — slope of −1 (constant P = V·I) for long pulses; relaxes for shorter pulses (transient thermal impedance).
For BJTs there is a fourth: secondary breakdown, a diagonal at steeper slope (typically −2 in log-log) that is much tighter than the thermal limit. It is caused by local hot-spots forming filaments of high current density; once they nucleate the device destroys itself in microseconds. Power MOSFETs are essentially immune to second breakdown because their channel resistance has a positive temperature coefficient (hot regions push current away). This is the single biggest reason MOSFETs replaced BJTs in linear pass-elements for HV regulators.
Gate-drive considerations
The MOSFET / IGBT gate is a capacitor (~1–100 nF) that needs to be charged through low impedance (typically 1–10 Ω) to fully turn on and off the device in tens of nanoseconds. Specific concerns:
- Miller plateau holds V_GS at threshold + (I_D/g_m) for the duration of the V_DS swing. During this plateau, all driver current goes into C_gd, none into C_gs. Reducing the plateau duration means a more powerful driver (higher source/sink current capability) or a smaller C_gd (lower Q_gd device).
- dV/dt-induced false turn-on: during fast V_DS swing at turn-off, current i = C_gd · dV/dt flows into the gate. If the gate driver’s pull-down impedance is too high, V_GS rises above V_th and the device turns back on — shoot-through across a half-bridge, instant destruction. Mitigation: drive V_GS to a negative off-voltage (−3 to −10 V for SiC, 0 V acceptable for Si IGBT, occasionally −2 V for Si MOSFET in critical designs).
- Gate resistor trade-off: lower R_g means faster switching (less loss) but more EMI and more ringing on V_DS overshoot at turn-off. Practical values: 1 Ω for ultra-fast SiC/GaN at low current, 5–10 Ω for typical TO-220 Si MOSFET, 20–100 Ω for slow IGBTs in EMI-sensitive applications.
Common circuit topologies
- Common emitter / common source — voltage amplifier, inverting, high gain. Workhorse small-signal stage.
- Emitter follower / source follower — unity-gain buffer, low output impedance. Output stage of every op-amp.
- Common base / common gate — current buffer, high input current impedance, low V output. Used in cascode for high-frequency response.
- Differential pair — two matched BJTs/MOSFETs sharing a tail current. Input stage of every op-amp and comparator; the basis of all analog IC design.
- Cascode — common-emitter feeding a common-base. Bootstraps r_o into the gain calculation, achieving voltage gain near a_v_intrinsic of the transistor.
- Totem-pole / push-pull — complementary NPN-PNP or NMOS-PMOS pair. Output stage that sources and sinks. Class AB biasing for low distortion.
- H-bridge — four switches arranged 0–V — load — V–0. Drives a DC motor or inductive load in either direction. Foundation of every BLDC drive, every audio class-D amplifier, every solar inverter (in 3-phase: a 3-leg variant).
7p. Edge cases & assumptions
Shockley equation is the ideal limit. Real diodes deviate at three regimes:
- Low current (sub-µA): generation/recombination in the depletion region adds a second term with ideality factor n ≈ 2, making the slope 120 mV/decade instead of 60 mV/decade.
- Mid current: the ideal n = 1 regime, 60 mV/decade, where Shockley works.
- High current: series resistance R_S of the contacts (typically 50 mΩ – 1 Ω) adds I·R_S to V_F, flattening the I-V curve. Above ~10× rated current, V_F rises linearly with I rather than logarithmically.
The 60 mV/decade slope assumes 300 K. At 400 K it would be 79.4 mV/decade. Diode-based current sources are temperature-sensitive — bandgap references exist precisely to cancel this out.
MOSFET square-law assumes long channel. For modern logic (< 100 nm channel) and high-V_GS in power devices, velocity saturation makes I_D scale linearly with V_GS − V_th. SPICE BSIM4/BSIM-CMG models handle this; hand calculation with the square-law overestimates I_D for low V_GS overdrive and underestimates for high overdrive.
Body diode is real. Every power MOSFET has a parasitic anti-parallel diode (the body-to-drain pn junction). It is slow (t_rr 50 ns – 1 µs in standard Si MOSFETs), and conducts when V_DS goes negative. Synchronous-rectifier topologies and bridge-driven inductive loads rely on this diode but pay for its t_rr — switching-loss bridges spend energy reverse-recovering the body diode every cycle. GaN devices have no minority-storage body diode (the “reverse-conduction” path through the channel has zero recovery), giving them a fundamental advantage in half-bridge topologies.
SOA at DC vs SOA at pulsed. The datasheet “DC SOA” curve is much tighter than the “single-pulse 100 µs SOA” curve. A linear regulator pass-element runs in the DC region; a switch operates in the pulsed region. Confusing them — applying pulsed-SOA to a linear application — has destroyed countless circuits.
Thermal runaway in paralleled BJTs. I_C has a positive temperature coefficient at constant V_BE (V_BE_on falls −2 mV/°C, so at the same V_BE the warmer device draws more I_C, dissipating more, getting still warmer). Without emitter-resistor ballast (0.1–1 Ω per BJT typical) paralleled BJTs cannot share current; one hogs everything and burns out. MOSFETs in parallel are self-balancing because R_DS(on) has a positive temperature coefficient (~+0.4 %/°C) — the hotter device sees more R, drops more V_DS, takes less I_D. This is another big reason MOSFETs replaced BJTs in high-current applications.
Avalanche-rated (UIS) MOSFETs. Standard MOSFETs that are reverse-biased past V_DS_max are destroyed in microseconds by avalanche breakdown. Modern “avalanche-rated” MOSFETs (Vishay TrenchFET, ON Semi FRFET, Infineon OptiMOS) are characterised to absorb a specific amount of unclamped-inductive-switching energy E_AS (typically 100 mJ – 5 J) — useful in low-side switch designs where transient overvoltage clamping is intentional. Always check E_AS rating before relying on this behaviour.
Wide-bandgap (GaN, SiC) caveats.
- dV/dt limits in gate driver: SiC MOSFETs switch V_DS at 30–100 kV/µs; common-mode currents through gate-driver isolation barriers (typically 50–100 pF) reach amps. Gate drivers need ≥ 50 kV/µs CMTI (common-mode transient immunity) rating; Si-IGBT drivers (10–25 kV/µs) are not adequate.
- Negative gate-bias requirement: SiC MOSFETs typically need V_GS_off = −3 to −5 V to prevent dV/dt-induced turn-on. GaN E-mode devices use 0 V off but have positive V_GS limit of only +6 V (vs +20 V for Si), so the gate driver must clamp tightly.
- PCB layout: with 1 ns switching edges, every nH of source-loop inductance creates a 1 V ringing per amp switched. Kelvin-source connections (separate path for gate-driver return current vs power-loop current) become mandatory above ~200 kHz GaN switching.
Datasheet vs textbook differences. The “typical” curves on a datasheet are not the same as worst-case design limits. β min on a 2N3904 datasheet is 100, “typical” β is 200, and the lot you receive may distribute β = 150–400. Always design for the min spec. Similarly, R_DS(on) on a MOSFET datasheet is quoted at T_j = 25 °C, V_GS = 10 V, and rises ~80 % at T_j = 100 °C, V_GS = 10 V; in a working design at 100 °C die temp the conduction loss is roughly 1.8× the textbook calculation.
8p. Tools & software
Circuit simulators (SPICE family):
- LTspice (Analog Devices, free, Windows/macOS) — the de-facto standard for analog and power-electronics hand-simulation. Massive built-in model library; fast convergence on switching circuits; rough schematic UI. Read manufacturer SPICE models (.subckt files) directly.
- ngspice (open-source, all platforms) — Berkeley SPICE3 derivative; engine inside KiCad’s simulator. CLI-driven with
.cirnetlists; reasonable nonlinear convergence. - PSpice / OrCAD (Cadence, commercial) — dominant in industrial analog design; deep vendor model integration; expensive seats.
- Spectre (Cadence, commercial) — analog and RF simulator of choice in IC design; PSS, HB, PNoise analyses for RF circuits.
- Synopsys Saber — commercial; mixed-signal and multi-physics (electrical + thermal + magnetic).
- PLECS (Plexim, commercial) — system-level power electronics simulator using piecewise-linear switch models; orders of magnitude faster than SPICE for converter and motor-drive systems where the focus is on control rather than device physics.
- Simulink + Simscape Electrical (MathWorks, commercial) — system-level; weakest at device-physics detail but strongest at controller co-simulation.
Device-physics simulators (TCAD):
- Synopsys Sentaurus TCAD — industry-standard 2D/3D drift-diffusion + hydrodynamic device simulator. Used by every semiconductor manufacturer for new-process development.
- Silvaco Atlas — competitor to Sentaurus; widely used in university research.
- COMSOL Semiconductor Module — multi-physics finite-element approach.
Thermal simulation:
- FloTHERM (Mentor / Siemens) — package- and board-level thermal CFD.
- 6SigmaET (Future Facilities / Cadence) — electronics-focused thermal CFD.
- Ansys Icepak — Ansys’s electronics-thermal solution; tight Ansys-suite integration.
Layout / schematic:
- KiCad (open-source) — schematic capture + PCB layout + integrated ngspice. Production-quality since v6.0.
- Altium Designer (commercial) — dominant in commercial PCB shops.
- Cadence Allegro (commercial) — high-end PCB layout for ASIC-package and HDI work.
Datasheet workflow: The datasheet is the contractual specification of a part — it overrules every textbook formula and every SPICE simulation. Read it carefully, in this order:
- Absolute maximum ratings — what destroys the part. Never exceed any of these ever.
- Recommended operating conditions — the design envelope.
- Electrical characteristics table — guaranteed numbers at specified conditions. Watch the footnotes — “typical” is informational, “min/max” is guaranteed.
- Typical characteristic curves — graphical “typical” behaviour over temperature, voltage, current. Useful for trends, not for limits.
- Application information / reference designs — manufacturer’s intended use; usually conservative but a safe starting point.
- Package thermal data — θ_JA, θ_JC, ψ_JT (top-of-package to junction).
Always cross-check manufacturer SPICE models against the datasheet — many vendor models are simplified and may not capture R_DS(on) vs temperature, reverse-recovery, or Miller plateau accurately enough for your design.
11. Cross-references
[[Engineering/circuit-analysis]]— prerequisite for everything in this note. Small-signal models linearise transistors back to the resistive networks analysed there.[[Engineering/op-amps]]— built internally from differential pairs (BJT or MOSFET) and current-mirror loads; understanding semiconductor devices makes op-amp imperfections (offset, drift, slew, GBW) calculable.[[Engineering/digital-logic]]— CMOS = paired NMOS+PMOS; propagation delay, dynamic power, leakage all reduce to MOSFET behaviour.[[Engineering/power-electronics]]— switching applications dominate semiconductor demand; converter topologies (buck, boost, LLC, three-phase inverter) are choreographed device switching.[[Engineering/microcontrollers]]— modern MCUs are 10⁶ – 10⁸ MOSFETs packed in 5–20 nm CMOS.[[Engineering/pcb-design]]— gate-drive loop layout, Kelvin-source connections, thermal vias and copper pours, current-loop area all matter at switching speeds.[[Engineering/electric-motors]]— every BLDC, PMSM, induction motor is driven by a MOSFET or IGBT three-phase bridge.[[Engineering/ac-analysis-three-phase]]— small-signal analysis of transistor stages uses phasor / impedance machinery from there.[[Robotics/power-systems]]— battery-to-motor BLDC drive chain is MOSFETs end to end.[[Robotics/comm-buses]]— photodiodes, Hall-effect, current-shunt amplifiers all rely on the device physics here.[[Languages/Tier3/hdl]]— SPICE netlist syntax for capturing, simulating, and stress-testing the circuits in this note.[[Languages/Tier3/hdl]]— analog hardware-description language for behavioural device models when SPICE models don’t exist or are too slow.[[Languages/Tier3/assembly-and-encoding]]— the silicon on which every instruction executes is exactly this material.[[Languages/Tier3/gpu-and-shaders]]— modern GPUs contain ~10¹⁰ MOSFETs; thermal and switching-loss math from this note set the power envelope.
12. Citations
- Sedra, A. S. & Smith, K. C. (2019). Microelectronic Circuits (8th ed.). Oxford University Press. The canonical undergraduate-through-graduate reference for semiconductor device modelling, hybrid-π and Ebers-Moll, and amplifier design.
- Razavi, B. (2016). Design of Analog CMOS Integrated Circuits (2nd ed.). McGraw-Hill. The standard graduate text for MOSFET-based analog IC design; deep on noise, mismatch, frequency response.
- Razavi, B. (2021). Fundamentals of Microelectronics (2nd ed.). Wiley. Undergraduate-level companion to the CMOS book.
- Mohan, N., Undeland, T. M. & Robbins, W. P. (2003). Power Electronics: Converters, Applications, and Design (3rd ed.). Wiley. The standard reference for switching-converter design and the device-selection trade-offs in section 6p.
- Hodges, D. A., Jackson, H. G. & Saleh, R. A. (2003). Analysis and Design of Digital Integrated Circuits (3rd ed.). McGraw-Hill. CMOS logic from the device-physics ground up.
- Pierret, R. F. (1996). Semiconductor Device Fundamentals (2nd ed.). Addison-Wesley (Modular Series on Solid State Devices). Compact, rigorous physics; companion volumes cover diodes, BJTs, MOSFETs separately.
- Streetman, B. G. & Banerjee, S. K. (2014). Solid State Electronic Devices (7th ed.). Pearson. Stronger physics foundation than Sedra/Smith; covers wide-bandgap and optoelectronic devices.
- Sze, S. M. & Ng, K. K. (2006). Physics of Semiconductor Devices (3rd ed.). Wiley-Interscience. The professional/research-grade reference for every device type ever made.
- Horowitz, P. & Hill, W. (2015). The Art of Electronics (3rd ed.). Cambridge University Press. Practical engineering judgement on transistor circuits — the chapter on “Mosfet vs BJT” alone is worth the book.
- Baliga, B. J. (2008). Fundamentals of Power Semiconductor Devices. Springer. Definitive on power-device physics, the R_on·A silicon-limit derivation, IGBT internals, and wide-bandgap power devices.
- Erickson, R. W. & Maksimović, D. (2020). Fundamentals of Power Electronics (3rd ed.). Springer. Companion to Mohan; stronger on converter dynamics and small-signal control.
- IEEE Std 100. The Authoritative Dictionary of IEEE Standards Terms. Reference for terminology used in datasheets and standards.
- JEDEC JESD22 family. Reliability Test Methods for Discrete Semiconductor Devices and Integrated Circuits. The qualification methodology behind every commercial part’s reliability claims.
- JEDEC JESD51 family. Methodology for Thermal Characterization of Semiconductor Packages. Specifies how θ_JA, θ_JC, ψ_JT are measured.
- MIL-STD-883. Test Method Standard, Microcircuits. Military / high-reliability test methods; aerospace qualification basis.
- AEC-Q100, AEC-Q101. Failure Mechanism Based Stress Test Qualification for ICs / Discrete Semiconductors. Automotive qualification standards.
- Manufacturer datasheets and application notes: Infineon (OptiMOS, CoolMOS, CoolSiC, IGBT4/5/7), Vishay (TrenchFET, SiBA), ON Semiconductor (FRFET, Power Integrations), STMicroelectronics (MDmesh, STPOWER SiC), Toshiba, Wolfspeed/Cree (SiC), GaN Systems (now Infineon), EPC (GaN). Always the first stop for ratings, models, and reference designs on a specific part.