Semiconductor Processing — IC Fabrication

1. At a glance

Integrated-circuit (IC) fabrication is the sequence of 500 to 1500 unit process steps performed on a single-crystal silicon wafer inside a Class 1 ISO 14644-1 cleanroom to build transistors, interconnect, and passivation layers. Modern leading-edge fabs run 300 mm wafers (12-inch, ~70,000 mm² of usable area each); 450 mm was officially cancelled by industry consortium G450C in 2017 after cost-of-ownership studies showed no economic benefit. Mature nodes (≥ 130 nm) still run on 200 mm; legacy MEMS, power, and analog often run 150 mm or 100 mm.

The 2026 leading-edge process landscape:

TSMC — N3 (3 nm FinFET, 2022 HVM), N3E (2023), N3P (2024), N2 (2 nm nanosheet GAA, 2025 risk → 2026 HVM), N2P, A16 (1.6 nm with backside power, 2026 risk).
Samsung Foundry — 3GAE (3 nm MBCFET nanosheet, 2022 HVM), 3GAP (2024), 2GAP (2 nm, 2025 ramp), SF1.4 (2027 target).
Intel Foundry — Intel 7 (10ESF, equivalent to others’ 7 nm, 2021), Intel 4 (EUV introduction, 2023), Intel 3 (2024), Intel 18A (1.8 nm with RibbonFET GAA + PowerVia BSPDN, 2025 HVM at Fab 52 Arizona / Fab 28 Israel).

EUV photolithography is supplied solely by ASML — the TWINSCAN NXE:3400B, NXE:3600D, and NXE:3800E systems run at 0.33 NA (180 wafers/hour throughput), while the new TWINSCAN EXE:5000 at 0.55 NA (“High-NA EUV”) shipped its first commercial systems to Intel in 2024 at roughly $380M per tool, supporting ~185 wph at 1 nm-class half-pitch.

Cost-of-ownership for a leading-edge greenfield fab: USD 20–40 billion for the fab shell + tools (TSMC Fab 21 Arizona: $40 B; S am s u n g T a y l or TX :$ 25B; Intel Ohio Mega-Fab: $28 B ini t ia lp ha se) . P er - t oo l :$ 380M EUV scanner, $50-80 M d e p os i t i o n c l u s t er t oo l,$ 5–15M etch chamber, $15-25 MCMP,$ 5–25M inspection.

2. Why it matters

The semiconductor industry is roughly USD 600–700 billion in annual revenue (2024–2026) and the substrate of every other digital, electrical, and modern mechanical system. The 2020–2023 AI inference boom, driven by NVIDIA H100/H200/B100/B200 GPUs built on TSMC N5/N4/N4P/N3, made fab capacity a geopolitical asset:

CHIPS and Science Act (US, 2022) — $52.7B in direct subsidies + 25% investment tax credit for US fab construction; targets at Intel Ohio, TSMC Arizona, Samsung Taylor, Micron Idaho/Syracuse, GlobalFoundries Malta.
EU Chips Act (2023) — €43B to double EU share of global chip production to 20% by 2030; ASML expansion, Infineon Dresden, Intel Magdeburg (paused 2024).
Japan METI — ¥2T+ for TSMC Kumamoto JASM Fab 1 (22/28 nm) and Fab 2 (6/7 nm), Rapidus 2 nm pilot line at Chitose Hokkaido (2027 target).
South Korea K-Chips Act, Taiwan Hsinchu and Kaohsiung expansions, China Big Fund III (¥344B mainland fund, 2024).

Beyond economics: the Taiwan Strait carries ~90% of leading-edge logic (TSMC) and ~70% of advanced packaging (CoWoS, InFO, SoIC). Strategic concentration drives the reshoring policies above.

Moore’s Law transistor-density doubling every ~2 years held from 1965 to roughly 2014 (22 nm node), then decelerated to ~3-year cadence. Continued performance scaling now comes from DTCO (Design-Technology Co-Optimization — coordinating standard-cell layout with process features) and STCO (System-Technology Co-Optimization — partitioning a die into chiplets on different process nodes, integrated through advanced packaging). Effective performance per dollar still rises, but per transistor economics inverted at N5/N3 — leading-edge cost-per-transistor stopped falling.

3. First principles — substrate and crystal

Wafer manufacturing — from sand to mirror-polished silicon

Czochralski (Cz) growth is the dominant boule-pulling technique. Molten electronic-grade polysilicon (99.9999999% pure — “9N”) is held at 1414 °C in a quartz crucible inside an argon-purged growth chamber. A small seed crystal of known {100} or {111} orientation is dipped into the melt, then slowly rotated and withdrawn (~1–2 mm/min vertical, 10–30 rpm rotational). Surface tension pulls a solid cylinder of single-crystal silicon — the boule — from the melt. Production boules: 300 mm diameter × 1.0–1.5 m long, mass 150–250 kg, ~20 hours growth time.

Float-zone (FZ) silicon is used for high-purity power and radiation-detector applications. A polycrystalline rod is held vertically; an RF coil locally melts a short zone that traverses the rod. Impurities segregate into the moving liquid and concentrate at one end. FZ silicon achieves resistivity > 10,000 Ω·cm and oxygen content < 1 × 10¹⁶ atoms/cm³ (Cz silicon is ~10¹⁸); essential for high-voltage IGBTs and SiC substrate seeds. Maximum FZ diameter ~200 mm (mechanical instability above this).

Wafer prep sequence (post-boule):

Crop — saw off the seed end and tail cone.
Grind — diamond-wheel cylindrical grind to nominal diameter (300.00 mm ± 0.20 mm per SEMI M1).
Orient and notch — X-ray Laue diffraction locates the crystallographic axes; a notch (SEMI M1) is ground at the {110} flat position for downstream alignment.
Wire saw — diamond-coated stainless steel wire (~150 µm dia) drawn through PEG-suspended SiC abrasive slurry; cuts ~600 wafers from a 1.5 m boule simultaneously. Kerf loss ~150 µm; resulting wafers ~775 µm thick.
Lap — both-side mechanical planarization with Al₂O₃ slurry; removes saw damage, planarizes to ±1 µm TTV.
Etch — HNO₃/HF/CH₃COOH chemical etch removes ~10 µm of subsurface damage from lapping.
CMP polish — final mirror finish on the device side; sub-nm RMS roughness over the 300 mm area.
Final clean — RCA sequence: SC1 (NH₄OH:H₂O₂:H₂O 1:1:5, 70°C — removes organics, metals) then SC2 (HCl:H₂O₂:H₂O 1:1:6, 70°C — removes alkali metals).

Final 300 mm wafer specs: thickness 775 ± 25 µm, TTV (total thickness variation) < 1 µm, bow < 30 µm, warp < 40 µm, particles > 65 nm < 50 per wafer, metals < 10¹⁰ atoms/cm².

Crystal orientations and their roles

Orientation	Notation	Primary use	Why
{100}	(100)	Bulk CMOS logic, DRAM, sensors	Maximum electron mobility for NMOS; {111} sidewalls from KOH etch enable MEMS
{110}	(110)	Strained-Si pMOS variants	~2.5× hole mobility vs (100); used in hybrid-orientation CMOS research
{111}	(111)	Discrete bipolar power, SiC epitaxy	Lower surface state density; SiC 4H polytype grown on (0001) Si face
GaN-on-Si (111)	—	Power GaN HEMTs	Lattice mismatch < 17%, manageable strain

Doping — introducing dopants

Ion implantation is the dominant doping technique since ~1985. A dopant gas (BF₃, PH₃, AsH₃, GeF₄) is ionized in a plasma source, accelerated by a high-voltage column (1–500 keV), mass-analyzed by a magnetic sector to select the desired isotope, and scanned across the wafer surface. Implant dose ranges 10¹¹ cm⁻² (threshold tweaks) to 10¹⁶ cm⁻² (S/D contacts). Dose uniformity ±0.5% across 300 mm.

Process parameters: B at 0.5–60 keV for shallow p-type; BF₂⁺ for very-shallow p; P at 5–200 keV; As at 5–100 keV (heavier ion, shallower for given energy); In at 30–500 keV (super-shallow halos); Ge for amorphization preconditioning. Post-implant annealing is mandatory to repair lattice damage and electrically activate dopants — historic furnace anneals (900–1100 °C for hours) are replaced by RTA / RTP (Rapid Thermal Processing, ~1000 °C for 10–60 s on lamp-heated tools) and millisecond / spike anneals (flash lamp or laser, 1200 °C for ~1 ms) to minimize dopant diffusion.

Diffusion doping (legacy) — wafers placed in a quartz furnace at 900–1100 °C in a dopant-bearing ambient (POCl₃ vapour for P, BBr₃ for B). Used pre-1985 and still common in bipolar power and solar.

In-situ doped epitaxy — dopant gas added to the silicon-precursor gas during CVD or LPCVD epi growth; produces atomically-abrupt junctions impossible with implantation. Used for SiGe pMOS S/D stressors, Si:C nMOS S/D, and SiC drift layers.

Epitaxy

Epitaxy is single-crystal growth of one material on top of another, with the new layer’s crystal lattice continuous with the substrate. Used to add lightly-doped layers on top of heavily-doped substrates (BJT collectors, CMOS latch-up suppression), to grow SiGe and Si:C stressor layers in S/D recesses, and to build SiC and GaN power-device structures.

CVD epi (Si, SiGe, Si:C) — SiH₂Cl₂ (dichlorosilane), SiH₄, or Si₂H₆ at 600–1100 °C; growth rate 0.1–1 µm/min. Applied Materials Centura RP-Epi and ASM Epsilon are the dominant production tools.
MOCVD (Metal-Organic Chemical Vapour Deposition) — trimethyl-gallium + NH₃ for GaN; for LED, RF GaN, power GaN-on-Si. Veeco TurboDisc, Aixtron Crius.
MBE (Molecular Beam Epitaxy) — ultra-high-vacuum (10⁻¹⁰ Pa) elemental-source evaporation; atomic-layer precision; used for III-V (GaAs, InP, InGaAs HEMT) and research-grade structures. Riber, Veeco GEN. Very slow (~µm/hour) and expensive; not for high-volume.

4. Photolithography — the heart of IC fab

Lithography is the patterning step that defines every feature on every layer. It accounts for 30–45% of total fab tool cost and is the rate-limiting step at every process node. The fundamental relation is Rayleigh’s equation:

R = k₁ · λ / NA

where R is half-pitch resolution, λ is exposure wavelength, NA is the lens numerical aperture, and k₁ is a process factor (theoretical floor 0.25; practical 0.27–0.40 with full RET). Depth of focus DOF = k₂ · λ / NA² — tightening trades off against DOF, which is why thinner resists and tighter wafer flatness become essential as NA rises.

Wavelength evolution

Era	Wavelength	Tool	Application	Half-pitch
1980s	g-line 436 nm	Hg-arc steppers (Nikon NSR-1010G)	1.5–1.0 µm CMOS	~500 nm
Late 1980s	i-line 365 nm	Nikon NSR-2005i, Canon FPA-3000i	0.5–0.35 µm	~350 nm
1990s	DUV 248 nm (KrF excimer)	ASML PAS 5500/300, Nikon S203B	0.25–0.13 µm	~120 nm
2000s	DUV 193 nm (ArF dry)	ASML PAS 5500/1100, Nikon NSR-S307	90–65 nm	~65 nm
2004–	DUV 193 nm immersion (water n=1.44)	ASML TWINSCAN NXT:1980Di, NXT:2050i, NXT:2100i	65–7 nm (with multi-patterning)	38 nm single-exposure
2019–	EUV 13.5 nm (0.33 NA)	ASML TWINSCAN NXE:3400B/3600D/3800E	7–2 nm	~16 nm single-exposure
2024–	High-NA EUV (0.55 NA)	ASML TWINSCAN EXE:5000, EXE:5200	2–1.4 nm	~8 nm single-exposure

EUV physics and engineering

EUV at 13.5 nm is absorbed by every material including air, all conventional glasses, and the resist itself. Engineering implications:

Vacuum-only beampath — entire optical column at < 10⁻³ Pa.
Reflective optics only — no refractive lenses; all-mirror Schwarzschild-style projection with Mo/Si multilayer reflective coatings (40 alternating ~3 nm layers, ~70% reflectivity per mirror, 6–10 mirrors per system → ~1–2% overall transmission).
Reflective masks — Mo/Si multilayer reflector on low-thermal-expansion-material (LTEM) ULE glass substrate with Ta-based absorber pattern; mask sits at 6° non-telecentric incidence.
Plasma light source — CO₂ laser-produced plasma (LPP) on Sn droplets; 250 kHz, ~250–500 W in-band power at intermediate focus. Cymer (ASML subsidiary) sole supplier. The droplet generator dispenses 30 µm Sn droplets at 50,000 per second.
Pellicle — protective membrane (recently polysilicon-CNT-based by ASML/Mitsui Chemicals, ~88–92% transmission) over the mask to prevent particle defects.
Resist — chemically-amplified resists (CAR) absorb only ~20% of incident EUV; metal-oxide resists (Inpria, JSR) absorb ~80%, with better LWR but worse shelf-life and contamination control.

Mask (reticle) technology

Mask type	Substrate	Pattern layer	Use
Binary COG (Chrome-on-Glass)	Quartz	Cr absorber	i-line, KrF non-critical layers
Att-PSM (Attenuated Phase-Shift Mask)	Quartz	MoSi (6% transmission)	ArF dry, ArFi non-critical
Alt-PSM (Alternating PSM)	Quartz	Cr + etched-quartz phase shifter	ArFi critical (now legacy)
OPC-corrected	Quartz	Cr or MoSi with sub-resolution assist features (SRAF)	Standard ArFi
EUV mask	LTEM (Schott Zerodur, Corning ULE)	Mo/Si 40-pair multilayer + Ta-based absorber	NXE:3400+

Mask write tools: Multibeam (NuFlare EBM-9000, IMS Nanofabrication MBM-101) — 250,000 parallel electron beams. Mask write times: 8–24 hours per critical EUV reticle.

Resist process — the full sequence for a single exposure

HMDS prime — hexamethyldisilazane vapor on the wafer; converts hydroxyl-terminated SiO₂ to hydrophobic, improving resist adhesion.
Spin coat — resist dispensed (~5 mL) on rotating wafer (1500–4000 rpm); film thickness 30–500 nm.
Soft bake (PAB) — 90–130 °C for 60–90 s; drives off casting solvent.
Expose — image projected from mask onto resist; dose 15–60 mJ/cm² (DUV CAR); 25–80 mJ/cm² (EUV CAR).
PEB (Post-Exposure Bake) — 100–130 °C for 60–90 s; drives chemical amplification reaction (the acid generated during exposure catalyzes deprotection of the polymer).
Develop — 0.26 N TMAH (tetramethylammonium hydroxide) on positive-tone resist; or organic solvent (n-butyl acetate) for negative-tone development; 30–60 s puddle.
Hard bake — optional 100–130 °C to densify resist before etch.
Etch — pattern transferred into underlying film.
Strip — O₂ plasma ash + wet (SPM: H₂SO₄:H₂O₂ “piranha”) to remove polymer residue.

Multi-patterning techniques

When λ/NA exceeds the desired half-pitch, the pattern is decomposed across multiple exposure-etch cycles:

LELE (Litho-Etch-Litho-Etch) — split features into two interleaved masks; exposure A → etch A → exposure B → etch B; halves the effective pitch. Risk: overlay between A and B directly degrades CD. Used widely at 14–10 nm.
LFLE (Litho-Freeze-Litho-Etch) — first exposure cross-linked thermally or chemically, second exposure aligned on top.
SADP (Self-Aligned Double Patterning) — pattern a mandrel, deposit a conformal spacer (ALD oxide or nitride), etch back to leave sidewalls, strip the mandrel. Final pitch = mandrel pitch / 2; overlay is now self-aligned. Default at 22/14/10 nm fin formation.
SAQP (Self-Aligned Quadruple Patterning) — two iterations of SADP; final pitch / 4. Used at 7 nm fin pitch (~30 nm).
SAOP (Self-Aligned Octuple Patterning) — three SADP iterations; 5 nm node demos.

Computational lithography

OPC (Optical Proximity Correction) — pre-distort the mask to compensate optical-system aberrations and proximity effects; serifs, line-end extensions, sub-resolution assist features (SRAFs). Synopsys Proteus, Siemens Calibre nmOPC.
ILT (Inverse Lithography Technology) — full inverse-problem optimization to find the mask that best produces the desired wafer image; computationally heavy (~1000 CPU-hours per mask). ASML Tachyon ILT, Synopsys Inverse Lithography.
SMO (Source-Mask Optimization) — joint optimization of source pupil shape and mask pattern.
MBOPC / model-based MPC — eBeam mask-correction.

5. Etching and thin-film deposition

Dry etching (plasma)

Dry etching uses a plasma (typically RF-coupled, 13.56 MHz at 100–3000 W) of reactive gases to chemically + physically remove material. Etch chemistries are layer-specific:

Material	Etchant gases	Tool family	Notes
Si (poly, single-crystal)	HBr / Cl₂ / SF₆ / NF₃	Lam Kiyo / 2300 Versys, AMAT Centura	Cl₂ for high aniso; SF₆ for high rate
SiO₂	C₄F₈ / CF₄ / CHF₃ / Ar	Lam Flex, AMAT eMax, TEL Tactras Vigus	Fluorocarbon polymer-mediated; contact + via etch
SiN	CHF₃ / SF₆ / NF₃	Same as above	Spacer + hard mask
Al / AlCu	Cl₂ / BCl₃ / N₂	Legacy AMAT P5000	Post-etch corrosion concern; mostly displaced by Cu damascene
Cu	Difficult (volatile compounds rare)	Damascene avoids Cu etch	Cu patterned by trench-fill + CMP
W	SF₆ / NF₃	Lam	Plug + bitline metal
HfO₂ (high-k)	BCl₃ / Cl₂	AMAT Centris, Lam	Selective to Si in HKMG flow
TiN / TaN (metal gate)	Cl₂ / BCl₃	Lam Versys Metal	Work-function metal patterning

Tool architectures:

RIE (Reactive Ion Etching) — parallel-plate diode; CCP (capacitively coupled plasma); legacy.
ICP (Inductively Coupled Plasma) — high-density plasma decoupled from wafer bias; independent control of density and ion energy. Standard for modern Si etch (Lam Kiyo, AMAT Centura DPS).
ECR (Electron Cyclotron Resonance) — microwave + magnetic confinement; ultra-high density.
CCP dual-frequency — separate plasma-generation and bias frequencies; standard for dielectric etch (Lam Flex, TEL Tactras).
ALE (Atomic Layer Etch) — self-limiting two-step cycle: surface modification (e.g., Cl₂ chemisorption) → low-energy Ar⁺ ion sputter removes only the modified layer. Sub-Angstrom precision; used for gate-channel definition at 5 nm and below. Lam pioneered (~2014 commercialization).
Bosch DRIE — alternating C₄F₈ passivation and SF₆ etch; high aspect ratio (30:1 routine, 100:1 demonstrated). Lärmer & Schilp, Bosch, US Patent 5501893 (1996). Primarily MEMS and TSV; not used for ICs.

Wet etching

Largely displaced from feature patterning by dry etching; still used for cleaning, photoresist strip, bulk material removal, and selective film removal:

HF (1–49% dilute) — oxide etch and clean; SC1/SC2 (RCA) precursor.
KOH (~30%, 80°C) — anisotropic silicon etch; {100}/{111} selectivity ~400:1; pyramidal sidewalls at 54.7°. Bulk MEMS, V-grooves.
TMAH (~25%, 90°C) — CMOS-compatible alternative to KOH (no K contamination).
H₃PO₄ (180°C) — selective nitride strip (SiN over SiO₂ ~ 100:1).
Piranha (H₂SO₄:H₂O₂ ~ 4:1) — organic strip after lithography.
APM, HPM, SPM — RCA clean variants.

Deposition

Method	Mechanism	Typical films	Tool vendors	Use
PVD (sputter)	Argon-ion bombardment of target	Ti, TiN, Ta, TaN, Al, Cu, W, Co, Ru	AMAT Endura, Lam Aplion	Liner/barrier, seed layers, metal interconnect
Evaporation	Thermal or e-beam	Au, Al, Cr (legacy)	Temescal, Denton	R&D, MEMS, packaging
APCVD	Atmospheric pressure CVD	SiO₂ (BPSG, PSG)	AMAT P5000 (legacy)	Pre-metal dielectric (mature nodes)
LPCVD (550–800°C)	Low-pressure thermal CVD	Polysilicon, SiN, undoped poly-Si, SiO₂	TEL Indy, ASM A412	Gate poly, spacer SiN, capacitor dielectric
PECVD (200–400°C)	RF-plasma CVD	SiO₂, SiN, SiON, a-Si, SiC, SiCN, low-k SiCOH (k=2.5–3.0)	AMAT Producer, Lam Vector, ASM Eagle	BEOL ILD, passivation, hard masks
SACVD (subatmospheric CVD)	Ozone-TEOS sub-atm	SiO₂ (gap fill)	AMAT HARP	Pre-metal gap fill
HDP-CVD	High-density plasma CVD with simultaneous sputter	SiO₂	AMAT Ultima	STI gap fill (legacy; replaced by FCVD + HDP combo)
FCVD (Flowable CVD)	Polymerize on surface, then cure	SiO₂	AMAT Eterna, ASM	High-AR STI gap fill at advanced nodes
ALD	Self-limited monolayer; alternating precursor pulses	HfO₂, ZrO₂, Al₂O₃, TiN, TaN, Ru, W, Co	ASMI Pulsar, AMAT Olympia, Lam ALD	High-k gate dielectric, metal liners, work-function metals
MBE / MOCVD	Epitaxial single-crystal	GaAs, GaN, InP, AlGaN, SiGe	Veeco, Aixtron, Riber	III-V; compound semi
Electroplating (ECD)	Aqueous electrochemical	Cu (damascene fill), Ni, Au, solder	AMAT SlimCell, Lam SABRE, NEXX	Cu BEOL, TSV, bump

ALD deserves emphasis: HfO₂ via tetrakis-dimethylamino-hafnium (TDMAH) + H₂O at 250–300 °C is the high-k gate dielectric used since the Intel 45 nm node introduction (Bohr et al., IEDM 2007) — the largest material transition in CMOS since the introduction of polysilicon gates. Equivalent oxide thickness (EOT) of ~0.9 nm with physical HfO₂ thickness ~2 nm.

6. Transistor architecture evolution

Era	Architecture	Channel control	Node range	Process driver	Originators
1970s–2000s	Planar bulk CMOS	Gate above planar inversion layer	10 µm – 32 nm	Lithography scaling	Wanlass & Sah 1963 (CMOS)
2007–	HKMG (High-k Metal Gate)	Same as planar; gate stack swap	45–22 nm	Gate leakage control	Intel 45 nm 2007 (Bohr/Mistry)
2011–	FinFET (Tri-gate)	3-sided gate over vertical Si fin	22 nm – 5 nm	Short-channel control	Hu, Bokor, King-Liu UC Berkeley 1999; Intel 22 nm 2011
2022–	GAA Nanosheet (MBCFET, RibbonFET)	4-sided gate around stacked Si nanosheets	3 nm – 1.4 nm	Improved electrostatics, V_t tuning	Samsung 3GAE 2022, TSMC N2 2025, Intel 18A 2025
~2030	CFET (Complementary FET)	Stacked nMOS over pMOS	1 nm and below	Layout area scaling	Imec roadmap
Research	2D TMD channels (MoS₂, WS₂, WSe₂)	Monolayer channel	Sub-1 nm	Ultimate scaling	Stanford, Imec, TSMC R&D
Long-term	Spintronics, photonics, neuromorphic	Non-CMOS	—	Beyond Boolean	—

FinFET introduction — Intel’s 22 nm tri-gate (Ivy Bridge, 2011) was the first commercial fin device, four years ahead of TSMC 16FF (2015) and Samsung 14LPE (2015). Fin pitch evolved from 60 nm (22 nm node) to 27 nm (5 nm node) — 12 fin generations in 10 years.

GAA Nanosheet — Samsung’s MBCFET (Multi-Bridge Channel FET, 3GAE 2022) was first; TSMC N2 (2 nm, 2025) and Intel 18A RibbonFET (2025) followed. Three stacked horizontal sheets (~5–6 nm thick × ~25–40 nm wide) wrapped in HKMG; sheet width is now a tunable parameter for V_t and drive-current binning. PowerVia / BSPDN (backside power delivery network) at Intel 18A routes power from the back of the wafer, leaving the front-side metal stack for signals only — a 5–8% area scaling plus reduced IR drop.

7. CMOS process flow (14 nm-class FinFET reference, ~700 steps)

A representative simplified flow — modern N2/18A GAA flows add ~200 more steps for sheet release and inner spacers.

Wafer in — 300 mm Cz Si, p-type, 6–10 Ω·cm.
STI (Shallow Trench Isolation) — pad oxide (LPCVD), SiN hard mask, photoresist pattern, etch trenches 250 nm deep, liner oxide, FCVD oxide fill, anneal, CMP planarize.
Well implant — n-well (P at 400–800 keV, ~10¹³ cm⁻²) for pMOS; p-well (B at 200–400 keV) for nMOS; through screen oxide; subsequent retrograde well implants for V_t tuning.
Fin patterning — SADP / SAQP with mandrel + spacer; final fin pitch 27–48 nm.
Fin reveal and etch — DRIE silicon, fin height 35–50 nm.
STI recess and fin reveal — selective oxide etch to expose fin sidewalls.
Channel epi — optional SiGe channel for pMOS (mole fraction 25–50%).
Gate-first dummy — deposit dummy polysilicon, SiN cap; pattern with EUV or SAQP-193i; etch.
Spacer + LDD — SiN spacer (ALD), LDD/extension implants (As for nMOS, BF₂ for pMOS).
S/D recess — etch ~30 nm into Si in S/D regions.
S/D epi — SiGe:B for pMOS (compressive stressor + in-situ B doping, 10²⁰ cm⁻³); Si:P or Si:C:P for nMOS (tensile stressor).
S/D activation — millisecond laser spike anneal at 1200 °C.
Silicide pre-amorphization — Ge implant.
Silicide formation — Ni or NiPt deposition, 350 °C RTA, selective wet strip; final NiSi or NiPtSi at S/D contacts.
ILD0 + CMP — interlayer dielectric.
Dummy gate removal — selective wet (NH₄OH) strips polysilicon.
HKMG (Replacement Metal Gate, RMG) — ALD interfacial SiO₂ + ALD HfO₂; ALD TiN (capping); work-function metals (Al, TiAl, TaAlC for nMOS; TiN for pMOS; multi-V_t binning via stack thickness); gate fill (W or Co).
Gate CMP.
MOL contacts — pattern + etch + Ti/TiN barrier + W plug + CMP.
BEOL (10–15 metal layers) — each layer: SiCOH low-k ILD (k=2.5–3.0; air gap research at k=1.5–2.0); dual-damascene pattern (via + trench in one); TaN/Ta barrier; Cu seed (PVD); Cu fill (electroplate); Cu CMP; cap (SiC, SiCN, or CoWP selective cap).
Bond pads + passivation — Al pad or Cu pillar; SiN passivation.
Wafer-level test (WLT, sort) — DC parametric + functional probe on every die.
Backgrind — thin to 50–150 µm (300 mm thinning challenge).
Dice (stealth dicing or blade).
Package — wire bond, flip-chip, or advanced (CoWoS, InFO, SoIC, HBM stacks).

CMP frequency: ~20–30 CMP steps interleaved across the flow. Ion implant: ~30–50 separate implant steps. Lithography: ~50–80 mask layers (a leading-edge logic flow has 80+ layers; ~10–15 use EUV at N5 and below, rising to 20+ at N3/N2). Defect inspection: at every critical step.

8. Cleanroom and metrology

ISO 14644-1 cleanroom classes

Class	Particles/m³ ≥ 0.1 µm	Particles/m³ ≥ 0.5 µm	Typical area
ISO 1	10	—	EUV scanner photocell, mask handling
ISO 2	100	—	EUV bay
ISO 3	1,000	35	DUV scanner bay, critical lithography
ISO 4	10,000	352	Track, develop, photo bay
ISO 5 (legacy Class 100)	100,000	3,520	General cleanroom, etch + deposition
ISO 6 (Class 1000)	1,000,000	35,200	Maintenance space
ISO 7 (Class 10,000)	—	352,000	Sub-fab

Air handling: vertical laminar flow at 0.45 m/s downward; HEPA / ULPA filters (99.99–99.9999% capture at 0.3 µm) in the ceiling occupying 60–100% of area; raised perforated floor with sub-fab return plenum. Air changes 300–600/hour. Temperature ±0.1 °C, humidity ±1% RH for lithography areas; ±0.5 °C, ±5% RH for general fab.

A modern 300 mm fab consumes ~300 MW electrical (cooling, tool power, sub-fab), ~40,000 m³/day of ultra-pure water (UPW, 18 MΩ·cm resistivity), and thousands of tons of process chemicals annually (H₂SO₄, HF, IPA, NH₄OH, H₂O₂, gases).

Inline metrology

Tool	Purpose	Vendors / models
CD-SEM	Top-down critical-dimension SEM	Hitachi CG6300, AMAT VeritySEM 7i, KLA eDR7380
Optical CD scatterometry	Pattern profile from spectral reflectance	KLA SpectraShape, Nova T600, Onto Atlas
Defect inspection (bright/dark-field)	Find pattern + particle defects	KLA 2935, 2925, 8935 (broadband plasma); AMAT Reflexion
e-Beam defect review (eBR)	High-resolution defect classification	AMAT SEMVision G7, KLA eDR
Ellipsometry	Film thickness + optical constants	J.A. Woollam M-2000, KLA Aleris 8810, Onto Atlas
XRR (X-Ray Reflectivity)	Film thickness + density + roughness	Bruker JVX, Rigaku SmartLab
Overlay metrology	Layer-to-layer registration	KLA Archer 750, ATL 100; ASML YieldStar 385
Wafer flatness / topography	Bow, warp, surface variation	KLA WaferSight, Onto Insight
AFM	High-resolution profilometry	Bruker Dimension Icon, Park NX-Hivac
TEM, EDX, XPS	Off-line cross-section, composition	Thermo Talos / Themis; Bruker EDX; Kratos XPS

Yield management

Yield Y is modeled as Y = exp(−A·D₀) (Poisson) or Murphy’s mixed model Y = ((1 − exp(−A·D₀))/(A·D₀))² where A is die area and D₀ is defect density (defects/cm² of all yield-killing types). At N5 a competitive D₀ is ~0.07/cm² for logic, giving Y ≈ 70% on a 100 mm² die. Per-layer D₀ Pareto drives yield-improvement engineering — typical critical layers have D₀ ~ 0.005–0.01/cm² individually.

The economics of chiplet partitioning: a 800 mm² monolithic die at D₀ = 0.1/cm² has Y ≈ exp(−0.8) ≈ 45%; four 200 mm² chiplets at the same D₀ each have Y ≈ exp(−0.2) ≈ 82%, and total assembly yield (4 × 82%) × interconnect yield (~99%) ≈ 53% — but the bad chiplets cost 1/4 each to discard. This drives NVIDIA Blackwell B200 dual-die, AMD MI300X chiplet, Intel Meteor Lake/Lunar Lake tile architecture.

9. Worked examples

Example A — Rayleigh resolution for EUV (0.33 NA and High-NA 0.55)

For the standard 0.33 NA ASML NXE:3600D EUV scanner at λ = 13.5 nm:

With aggressive single-exposure RET (k₁ = 0.40): R = k₁·λ/NA = 0.40 × 13.5 nm / 0.33 = 16.4 nm half-pitch
With ILT + SMO (k₁ = 0.30): R = 0.30 × 13.5 / 0.33 = 12.3 nm half-pitch

For the High-NA ASML EXE:5000 at 0.55 NA:

k₁ = 0.30: R = 0.30 × 13.5 / 0.55 = 7.4 nm half-pitch
k₁ = 0.25 (theoretical floor): R = 6.1 nm half-pitch

This is what supports the “1 nm node” naming convention — actual minimum metal pitches at the 1.4–1.0 nm marketing nodes are ~20 nm (M0) and ~14 nm (M1 with LELE on top of high-NA single-print).

Depth of focus at 0.55 NA: DOF = k₂·λ/NA² = 0.5 × 13.5 nm / 0.55² = 22 nm — about 3× tighter than 0.33 NA, demanding tighter wafer flatness and thinner resist.

Example B — Boron ion-implant dose and beamline throughput

Target: peak ¹¹B concentration of 1 × 10¹⁹ cm⁻³ at Rp = 20 nm depth in (100) Si.

From SRIM / Pearson IV moments tables: B at 5 keV in Si has Rp ≈ 21 nm with straggle ΔRp ≈ 12 nm. Peak concentration from a Gaussian profile:

C_peak = Dose / (√(2π) · ΔRp) ⇒ Dose = C_peak · √(2π) · ΔRp = 1e19 · 2.51 · 12e-7 = 3.0 × 10¹³ cm⁻²

(For deeper / heavier conditions the dose scales accordingly; for a contact implant at 10²⁰ /cm³, dose climbs to ~5 × 10¹⁴ cm⁻².)

Wafer throughput on a high-current implanter (Axcelis Purion XEmax) with 5 mA B⁺ beam at 5 keV:

Charge per wafer = Dose × q × A_wafer = 3.0e13 × 1.6e-19 × 707 cm² = 3.39 × 10⁻³ C

Time per wafer = Q / I = 3.39e-3 C / 5e-3 A = 0.68 s of beam time

Tool throughput including handling: ~300 wph at this dose; tool runs 24/7 and processes ~7,200 wafers/day per chamber.

Example C — Copper damascene via resistance

Trench: 30 nm wide × 80 nm deep; via: 30 nm × 100 nm (height between metal levels).

Liner stack: TaN 2 nm + Ta 1.5 nm + Cu seed 5 nm via PVD, then electroplate Cu to overfill, CMP back to liner.

Bulk-Cu resistance at 25 °C (ρ_Cu = 1.68 × 10⁻⁸ Ω·m):

R = ρ · L / A = 1.68e-8 · 100e-9 / (30e-9 × 30e-9) = 1.68e-15 / 9e-16 = 1.87 Ω

But at sub-50 nm cross-section, electron surface scattering and grain-boundary scattering dominate. The Fuchs-Sondheimer + Mayadas-Shatzkes model gives effective resistivity ρ_eff ≈ 2.5–3.5 × ρ_bulk for a 30 nm Cu trench (the “Cu resistivity size effect”). Effective R ≈ 4.7–6.5 Ω per via — and 100s of vias in series on a critical net add tens of mV of IR drop. This is the principal driver behind:

Cobalt liner / Co fill at 7 nm (resistivity ~5.6 × 10⁻⁸ Ω·m bulk; smaller mean free path → less degradation at sub-30 nm pitch).
Ruthenium for sub-5 nm contact metallization.
Backside power delivery (PowerVia) at Intel 18A — removes power rails from the BEOL critical path entirely.

10. Major fab equipment vendors

Segment	Market leaders	Notes
Lithography	ASML (~80% rev, sole EUV); Nikon, Canon (DUV + i-line)	ASML market cap > USD 280B (2025); 8-year EUV monopoly
Etch	Lam Research (~46%), AMAT (~22%), Tokyo Electron (~26%)	Lam Kiyo for Si; AMAT Sym3 + Centura; TEL Tactras
Deposition (CVD/PVD/ALD)	AMAT (~40%), Lam (~25%), TEL (~14%), ASM Intl (~12%, ALD leader)	AMAT Endura (PVD), Producer (PECVD), Centura (epi); Lam Vector (PECVD), ALTUS (W ALD)
CMP	AMAT Reflexion (~70%), Ebara F-REX (~25%)	KLA + others minority
Ion implant	AMAT Varian VIISTA / Quantum (~70%), Axcelis Purion (~25%)	High-current vs medium-current vs high-energy splits
Thermal (RTP/Furnace)	AMAT Vantage (RTP), TEL TELINDY, Hitachi Kokusai, ASM A412 furnace	Spike + flash + laser anneal
Cleaning + wet	TEL CELLESTA + CLEAN TRACK ACT, SCREEN FC-3300, Lam EOS	Single-wafer wet replacing batch
Metrology + inspection	KLA (~52%), AMAT (~13%), Hitachi (~9%), Onto Innovation, Bruker	KLA dominant in defect inspection + overlay
Mask write	NuFlare (TEL group), IMS Nanofabrication (Intel-owned)	eBeam multibeam writers
Assembly/Test	ASM Pacific (back-end), Kulicke & Soffa, BE Semiconductor, Teradyne (test), Advantest	Equipment for OSATs

SEMI E-series standards (E10 equipment efficiency / OEE, E30 GEM/SECS-II software interface, E90 substrate tracking, E120 CIM framework) define how all these tools interoperate in a fab MES.

11. Edge cases and gotchas

Line edge roughness (LER) and line-width roughness (LWR) — at <20 nm CD, stochastic resist defects + sidewall scallops become significant. 3σ LWR of 2–3 nm on a 20 nm feature is 15% variation, which directly hits V_t variation.
CD uniformity (CDU) budget — 3σ < 10% of nominal CD; for EUV at 20 nm CD that’s a 2 nm 3σ budget allocated across scanner (overlay, dose, focus), resist (LWR), and etch.
Stochastic EUV failures — at low photon dose, statistical fluctuation in photon count and acid-generation per resist molecule causes random bridging or open defects at parts-per-billion level. Drives the move to higher dose (~80 mJ/cm²) and metal-oxide resists.
EUV pellicle thermal management — pellicle absorbs ~12% of the EUV; at 500 W source power it sees ~60 W heat load on a few-mg membrane; rises to ~500 °C in steady state. Mechanical failure (rupture) is a known scanner downtime mode.
Defect density × area exponential yield drop — single 30 nm Cu particle on a critical contact layer is a kill defect; cleanroom particle counts must be Class 1 in EUV photocells.
Plasma damage to gate oxide — antenna effect: a long polysilicon line connected to a small gate accumulates plasma charge during etch; can rupture HfO₂ gate dielectric. Mitigated by antenna diodes at the gate node and by antenna ratio rules in DRC.
Cross-contamination control — Cu, Co, Ni, Au, alkali metals are catastrophic for MOSFET reliability if they reach the gate or active region. Cu-front-end isolation is absolute: separate clean stations, dedicated wet benches, separate operator garments in some fabs.
Plasma-induced damage (PID) / charging — ICP plasmas can deposit several volts of charge on floating gate metal; metal-gate is grounded via S/D extensions to mitigate.
Thermal budget — every high-temperature step diffuses dopants. Once a junction is set, total thermal budget is constrained to ~10⁻¹¹ cm² in (D·t). RMG flow puts HKMG after S/D activation specifically to allow ultra-shallow junctions and bypass the high-k thermal-stability limit.
Wafer warpage and overlay — thick BEOL Cu + low-k ILD + heavy underbump metallization introduce up to 200 µm of bow on a thinned 300 mm wafer. Drives overlay corrections in scanner control.
Reliability failure modes:
- TDDB (Time-Dependent Dielectric Breakdown) — HfO₂ wear-out, FOM target ~10 yr at use voltage with 1 ppm fail.
- NBTI / PBTI — Negative/Positive Bias Temperature Instability; V_t shift under DC stress; ~50 mV over 10 yr is the rough budget.
- HCI (Hot Carrier Injection) — high-field interface degradation in MOSFETs.
- Electromigration (EM) — Cu atom drift under current density; Blech length, void formation at vias; design current density limit ~1 MA/cm² at 100 °C.
Hazardous chemistry — HBr (etch), Cl₂, BCl₃ (etch), SiH₄ (CVD, pyrophoric), AsH₃ (epi, lethal at ppm), PH₃, ClF₃ (chamber clean, extremely reactive), TEOS, DMAH (high-k precursor). All require extensive abatement, gas scrubbers, monitored gas cabinets with double containment.
Cycle time — 60–90 days through the fab; 700–1000 process steps with average dwell time of ~2 h. WIP balancing across bottleneck tools (litho, implant) drives fab scheduling MES algorithms.
End-of-line wafer scrap cost — at N3 a fully-processed 300 mm wafer represents ~ $50, 000 in d e p os i t e d v a l u e; a s in g l e l a yer f ai l o na cr i t i c a lE U V e x p os u rec an scr a p an e n t i re l o t o f 25 w a f ers ($ 1.25M).
High-NA EUV mask shrinkage — at 0.55 NA the mask is exposed at 8× demagnification (vs 4× for 0.33 NA), but the mask itself remains 6-inch quartz; full-die patterning requires mask stitching across two exposures. Active research area at TSMC/Intel/Samsung.

12. Tools and software

TCAD (process + device simulation)

Synopsys Sentaurus — TSuprem4 / Athena (process); Sentaurus Device / Atlas (device); Sentaurus Lithography (mask + resist).
Silvaco Victory + Atlas — competing TCAD suite; popular in compound-semi.
Coventor SEMulator3D (Lam-owned) — virtual fab; full-process 3D voxel simulation for DTCO and integration studies.
COMSOL Semiconductor Module — finite-element drift-diffusion + Poisson for academic work.

Lithography simulation / OPC / ILT

Synopsys Proteus (formerly Mentor Calibre nmOPC ported in part) — model-based OPC.
Siemens / Mentor Calibre nmOPC + nmDRC — industry-standard OPC + DRC for sub-7 nm.
ASML Tachyon ILT — inverse-lithography for EUV.
KLA PROLITH — full vector imaging + resist simulation for R&D.
Cadence Pegasus / Mentor Calibre nmLVS / nmDRC — sign-off design rule checking + layout-vs-schematic.

Mask design + EDA (full chain)

Cadence Virtuoso + Innovus — analog + digital implementation.
Synopsys Custom Compiler + IC Compiler II — full RTL → GDS flow.
Siemens Calibre — DRC, LVS, OPC, RET sign-off.
Output: GDSII (1971-era, still dominant) and OASIS (newer, ~10× smaller files at advanced nodes).

MES + APC

Applied Materials APF + AMHS — fab automation, AMHS = automated material handling system (overhead-track foups).
Camstar / Siemens Opcenter Execution Semiconductor — MES, lot tracking, recipe management.
KLA Production Equipment Suite + Klarity — yield analysis + defect Pareto.
PEER Group ConnectionWorks — equipment connectivity, SECS/GEM standard.
Onto Innovation 8i / TruShape / Discover — metrology + APC.

Process simulation (specialty)

Coventor MEMS+ + SEMulator3D — coupled-domain MEMS + general fab.
Lumerical FDTD — photonic + EUV optics.
Crosslight / Genius — compound-semi device + process.

13. Cross-references

[[Engineering/semiconductor-devices]] — Tier 1 foundation: MOSFET / BJT / diode physics that this fab process produces.
[[Engineering/digital-logic]] — what gets built on top of the transistors fabricated here.
[[Engineering/mems]] — companion Tier 2; many shared process steps (DRIE, oxide, ALD) but with release + bonding additions.
[[Engineering/microfluidics]] — uses the same photolithography tooling for soft-lithography masters.
[[Engineering/pcb-design]] — packaging interface between chip + system; flip-chip, BGA, advanced packaging.
[[Engineering/materials-ceramics]] — HfO₂, ZrO₂, SiO₂, SiN, Al₂O₃ are the dielectric materials of the process.
[[Engineering/fluid-mechanics]] — gas-phase flow in CVD/ALD chambers; Knudsen-regime considerations.
[[Engineering/heat-transfer]] — millisecond anneal physics, RTP lamp coupling, chuck cooling.
[[Engineering/reliability-engineering]] — TDDB, EM, HCI, BTI; Weibull + lognormal lifetime modeling.
planned [[Engineering/photonics]] — EUV plasma source, silicon photonics co-fabrication, optical interconnects.
planned [[Engineering/power-electronics]] — SiC / GaN / Si fabrication intersection with power-device design.
[[Languages/Tier3/hdl]] — GDSII, OASIS, Verilog, SystemVerilog, SDF, SPEF, LEF, DEF interchange.

14. Citations

Plummer, J. D., Deal, M. D. & Griffin, P. B. (2000). Silicon VLSI Technology: Fundamentals, Practice, and Modeling. Prentice Hall. The canonical Stanford process-engineering text.
May, G. S. & Spanos, C. J. (2006). Fundamentals of Semiconductor Manufacturing and Process Control. Wiley-IEEE Press. Statistical process control + APC.
Quirk, M. & Serda, J. (2017). Semiconductor Manufacturing Technology (2nd ed.). Pearson. Operator-level reference; widely used in industry training.
Wolf, S. (1986–2002). Silicon Processing for the VLSI Era (5 volumes). Lattice Press. The encyclopedic process-physics reference.
Wong, H., Hu, C. & Mansfield, S. (2018). Fundamentals of EUV Lithography. SPIE Press.
Mack, C. (2007). Fundamental Principles of Optical Lithography: The Science of Microfabrication. Wiley.
Sze, S. M. & Ng, K. K. (2007). Physics of Semiconductor Devices (3rd ed.). Wiley. Device-physics companion to processing.
Bohr, M. T., Chau, R. S., Ghani, T. & Mistry, K. (2007). The high-k solution. IEEE Spectrum, 44(10), 29–35. Intel 45 nm HKMG introduction.
Hisamoto, D., Hu, C., Bokor, J., King, T.-J. et al. (1999). A folded-channel MOSFET for deep-sub-tenth micron era. IEDM Tech. Digest. UC Berkeley FinFET originator paper.
Lärmer, F. & Schilp, A. (1996). Method of anisotropically etching silicon. US Patent 5501893 (Robert Bosch GmbH). Bosch DRIE.
TSMC Symposium technical papers (2023, 2024) — N3, N3E, N2 process disclosures.
Intel Foundry IFS Direct Connect (2024) — Intel 18A RibbonFET + PowerVia disclosure.
Samsung Foundry Forum (2022, 2023) — 3GAE MBCFET, 2GAP roadmap.
ASML Annual Report 2024 + EUV roadmap white papers (asml.com).
ITRS (International Technology Roadmap for Semiconductors) 2015 final edition.
IRDS (International Roadmap for Devices and Systems) 2022, 2023 editions (irds.ieee.org).
SEMI standards: M1 (silicon wafer), M59 (wafer flat / notch), E10 (equipment efficiency), E30 (GEM/SECS-II), E90 (substrate tracking), F30 (facility), F47 (voltage-sag immunity).
ISO 14644-1:2015 Cleanrooms and associated controlled environments — Part 1: Classification of air cleanliness by particle concentration.
ASTM F1188 / F1392 silicon wafer specifications.
IEC 60749-series component-reliability tests; JEDEC JESD22 environmental tests; JEDEC JESD47 stress-test-driven qualification.
AEC-Q100 (automotive IC qualification).

Compendium

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Semiconductor Processing — IC Fabrication — Engineering Reference