Semiconductor Packages — Family Index

A semiconductor package is the mechanical/electrical/thermal interface between a silicon die and the printed-circuit board. Package selection drives I/O count, signal integrity, thermal performance, manufacturability, cost, and end-product form factor. The history of IC packaging is a story of lead-pitch reduction: from the 100 mil (2.54 mm) DIP of the 1960s, to 50 mil (1.27 mm) SOIC of the 1980s, to 0.5 mm QFN/BGA of the 2000s, to 0.35 mm WLCSP of the 2010s, with fan-out and 2.5D/3D integration carrying the trend further.

1. At a glance

Package categories, organized by lead-style and packaging level:

• Through-hole (THT) — leads pass through plated holes in the PCB: DIP, SIP, ZIP, PGA, TO-92, TO-220, TO-247, TO-3. Cheap to hand-solder; bulky; declining since the 1990s except for power and connectors.
• Surface-mount leaded (SMD-L) — gull-wing or J-leads soldered onto pads: SOIC, SOP/SOP, TSSOP, SSOP, MSOP, SOT-23, SOT-89, QFP/TQFP/LQFP. Workhorse from late 1980s onward.
• Surface-mount leadless (SMD-NL) — solder pads on the package perimeter and/or underside: QFN, DFN, LGA, BGA. Dominant for modern small-to-mid I/O ICs.
• Wafer-level CSP (WLCSP) — bumps formed at wafer level, then diced; package size ≈ die size; pitch 0.35–0.5 mm; used in modern mobile RF, PMICs, sensors.
• Fan-out wafer-level package (FOWLP / FOPLP) — reconstituted wafer/panel with embedded die plus redistribution layer (RDL) over molded surface; finer pitch than substrate-based packages.
• Die-down / flip-chip — die flipped face-down with solder bumps onto interposer or substrate; FCBGA, FCCSP.
• System-in-Package (SiP) — multiple die plus passives in one package: RF front-end modules, GPS+IMU modules, Wi-Fi/BT modules.
• Package-on-Package (PoP) — one package stacked atop another (DRAM-over-AP, used in smartphones).
• Chip-on-Board (COB) — bare die wire-bonded directly to PCB and globbed with epoxy; cheap calculator/toy ICs.

Driver across all categories: lead-pitch shrinking from 100 mil DIP to <0.4 mm WLCSP — driven by I/O density per silicon area, signal integrity at GHz speeds, and end-product miniaturization.

2. Through-hole packages

DIP (Dual In-line Package)

• 100 mil (2.54 mm) pitch, two rows of leads.
• 4 to 64 pins typical (8/14/16/20/24/28/40 most common).
• PDIP — plastic-encapsulated, low cost.
• CDIP — ceramic with metal lid, hermetic; military/aerospace; expensive.
• CERDIP — ceramic with glass seal.
• SDIP — shrink-DIP, 70 mil (1.778 mm) pitch — Japanese variant for higher pin counts in same body width.
• Iconic packages: 555 timer DIP-8, 7400-series TTL DIP-14/16, 8051 microcontroller DIP-40, original 8088 / Z80 / 6502 microprocessors DIP-40.

SIP / ZIP (Single / Zig-zag In-line)

• Single-row pins (SIP); zigzag-arranged single row (ZIP).
• Used for resistor networks and some DRAM modules in the 1980s.

PGA (Pin Grid Array)

• 2D grid of pins underneath the package; 100 mil or 50 mil pitch.
• Variants: CPGA (ceramic), PPGA (plastic), CLGA-prep (land-grid contacts replacing pins).
• Examples: Intel Pentium III PGA370, AMD Athlon Socket A/462, AMD AM4 (PGA-1331, the last mainstream PGA — 2017–2022). After AM5, AMD moved consumer CPUs to LGA.

TO-92 / TO-220 / TO-247 / TO-3

• TO-92 — small molded plastic, 3 leads radial, low-power transistors (2N3904, BC547).
• TO-220 — medium-power, 3 or 5 leads, metal tab for heat-sinking; 5-pin variants TO-220AB; common for 1–100 W MOSFETs and 7805-style regulators.
• TO-247 — larger than TO-220, higher-power MOSFETs and IGBTs (200–500 W class).
• TO-3 — old metal-can power package (TIP3055, 2N3055 BJT).
• TO-263 (D²PAK) and TO-252 (DPAK) — SMT variants of TO-220 with bent-down tab.
• TO-3P, TO-264 — larger axial variants.

3. Small-outline surface-mount leaded

SOT family (small-signal)

• SOT-23 — 3-pin, 0.95 mm pitch, body 2.9 × 1.3 mm; ubiquitous for jellybean transistors and SOT-23-5 / SOT-23-6 for op-amps and small ICs.
• SOT-89 — 3-pin, medium power (~0.5 W), 4.5 × 4.0 mm body with copper pad underneath.
• SOT-323 / SC-70 — smaller still (2.0 × 1.25 mm, 0.65 mm pitch).
• SOT-553 / SC-89 / SC-70-6 — micro-packages for analog switches and signal-line ICs.

SOP / SOIC family (medium I/O)

• SOIC — Small Outline IC, 1.27 mm (50 mil) pitch, gull-wing leads.
• SOIC-8 / SOIC-14 / SOIC-16 — the IC workhorse from late 1980s to 2000s.
• SOIC narrow (3.9 mm body) vs SOIC wide (7.5 mm body) — JEDEC MS-012 (N) and MS-013 (W).

Shrink-outline (sub-1.27 mm)

• SSOP — 0.635 mm pitch.
• TSSOP — Thin SSOP, 0.65 mm pitch, body 1.1 mm thick.
• MSOP-8 / MSOP-10 — 0.65 mm pitch, ultra-small.
• VSSOP — Very-thin Shrink SOP.
• QSOP — Quarter-Size Outline Package, 0.635 mm.
• HSOP / HTSSOP — heat-sinked variants with exposed pad.

Pin counts across the SOP family: 8 to 64 typical.

4. Quad packages

QFP (Quad Flat Pack)

• Four-sided gull-wing leads.
• Pitch: 0.65 / 0.5 / 0.4 mm typical.
• Pin counts: 32 to 256+ pins.
• Body sizes 7×7 mm to 40×40 mm.

QFP variants

• TQFP — Thin QFP (1.4 mm thick).
• LQFP — Low-profile QFP (1.4 mm thick, slightly different lead trim from TQFP).
• VQFP — Very-thin QFP (1.0 mm).
• PQFP — Plastic QFP (older 1980s naming).
• MQFP — Metric QFP.
• HQFP / HTQFP — heat-sink variants.

QFP dominated microcontroller and FPGA packaging in the 1990s and is still used for high-pin-count parts under 200 pins where BGA isn’t justified.

5. Leadless / no-lead

QFN (Quad Flat No-leads)

• The dominant modern small-IC package.
• Solder pads around perimeter on package underside, plus an exposed thermal pad in the center.
• Pitch: 0.5 / 0.4 / 0.35 mm.
• Pin counts: 16 to 100+ pins.
• Body sizes 3×3 mm to 12×12 mm.
• Variants: VQFN (very thin, 0.5 mm thick), TQFN, MR-QFN (multi-row), wettable-flank QFN for AEC-Q100 automotive (allows AOI of solder joint).
• JEDEC outline MO-220.

DFN (Dual Flat No-leads)

• Two rows of pads (long sides only); 6–10 pins typical.
• Used for op-amps, small power-management ICs, MOSFETs.

DSBGA / chip-array

• Die-size BGA-like packages.

6. BGA — Ball-Grid Array

History and major variants

• PBGA — Plastic BGA, introduced by Motorola in 1989 with the MC68340.
• FBGA — Fine-pitch BGA (0.8 mm or below).
• CBGA — Ceramic BGA.
• FCBGA — Flip-Chip BGA — die flipped face-down onto substrate, then balls on the underside; used for CPUs and GPUs.
• TBGA — Tape BGA — flexible substrate.
• CSP — Chip-Scale Package, ball pitch 0.4–0.5 mm, body within 1.2× die area.
• MicroBGA — 0.4 mm or 0.35 mm pitch.

Ball counts and pitches

• Small: 64–144 balls at 0.8 mm.
• Medium: 256–500 balls at 0.8 mm.
• Large CPU/GPU: 1000–6000+ balls at 1.0 / 0.8 mm.
• Typical pitch progression: 1.27 → 1.0 → 0.8 → 0.65 → 0.5 → 0.4 mm.

CPU sockets

• LGA — Land-Grid Array — pads on package, pins in the socket.
• Intel: LGA-775 (2004 Pentium 4), LGA-1156, LGA-1366, LGA-1155, LGA-1150, LGA-2011, LGA-1151, LGA-1200, LGA-1700 (12th-gen Core, 2021), LGA-1851 (14th-gen onward).
• AMD: Threadripper TR4 / sTRX4 (4094-land); AM5 LGA-1718 (since 2022, replacing AM4 PGA).
• Server: Intel LGA-2066 / LGA-4189 / LGA-4677; AMD SP3 (4094), SP5 (6096), SP6 (4844).

7. Wafer-level CSP (WLCSP)

• Bumps applied at wafer level via electroplating or stencil printing.
• Wafer is diced after bumping, yielding a chip whose footprint equals the die.
• Pitch 0.35–0.5 mm; body sizes from 1×1 mm up to ~6×6 mm.
• Common pin counts: 4 (e.g., Skyworks small RF switches) up to ~100.
• Heavy use in: mobile RF (front-end switches, LNAs, PAs), power-management (TI / Renesas PMICs), small sensors (ambient-light, temperature).
• Trade-offs: minimum board-level reliability (BLR) due to CTE mismatch between silicon die and FR4 board; underfill often required for handsets.

8. Fan-out wafer-level (FOWLP / FOPLP)

• Origin: TSMC’s InFO (Integrated Fan-Out) launched in mass production with Apple’s A10 in 2016 (iPhone 7).
• Process: dies are picked-and-placed onto a carrier (wafer or panel), molded into a reconstituted “wafer”, then RDL (redistribution layer) is built up over the mold to fan out I/O beyond the die edge.
• FOPLP (Fan-Out Panel-Level Packaging) — same concept on rectangular panels (typically ~300×300 mm or larger); better material utilization than circular wafers. Samsung, ASE, Powertech invested heavily 2018+.
• Advantages over flip-chip BGA: thinner profile, finer RDL pitch (2 µm line/space achievable), better electrical (shorter interconnects), no organic substrate needed.
• Used in: smartphone APs, RF FEMs, automotive radar SoCs.

9. 3D and advanced packaging

TSV — Through-Silicon Via

Vertical metallized via etched through the silicon substrate; enables die-to-die stacking with sub-µm pitch interconnect. HBM (High-Bandwidth Memory) stacks since 2015 use TSVs.

2.5D interposer

• Silicon interposer (passive die with RDL and TSVs) carries multiple active dies side-by-side.
• First major product: Xilinx Virtex-7 2000T (2011) with 28 nm FPGA on TSMC CoWoS.
• NVIDIA P100/V100/A100/H100 GPUs use 2.5D for HBM stacks on CoWoS.
• AMD Fiji (2015, Radeon R9 Fury X) was first GPU shipped with HBM via 2.5D.
• TSMC: CoWoS (Chip-on-Wafer-on-Substrate).

Intel EMIB

Embedded Multi-die Interconnect Bridge — a small silicon bridge embedded in the substrate connecting only the I/O regions of adjacent dies, avoiding a full-area interposer. Used in Stratix 10, Sapphire Rapids Xeon.

Foveros — Intel 3D die-stacking

• 2019: Lakefield mobile SoC — first commercial Foveros product (compute tile stacked on base die).
• 3D face-to-face bonding with µ-bumps (~50 µm pitch), evolving toward hybrid bonding (Cu-Cu, sub-10 µm).
• Foveros Direct and Foveros Omni for advanced nodes.

Chiplets and UCIe

• Chiplet trend: AMD’s “Zen 2” Ryzen 3000 (2019) was first mass-market consumer chiplet design — Core Complex Dies (CCDs) connected to an I/O die over substrate routing.
• UCIe — Universal Chiplet Interconnect Express, spec published 2022 by Intel/AMD/TSMC/Samsung consortium. Defines die-to-die PHY and protocol layer for cross-vendor chiplet interoperability.
• TSMC’s 3DFabric umbrella covers SoIC (3D), CoWoS (2.5D), and InFO (fan-out).

10. Power and discrete packages

Through-hole power

• TO-220 (3-lead and 5-lead variants).
• TO-247 / TO-3PN — higher power MOSFETs and IGBTs.
• TO-3 — old metal-can, isolated mounting.
• TO-264 — TO-247 variant.

SMT power

• D²PAK (TO-263) and DPAK (TO-252) — bent-leg SMT TO-220 cousins.
• TO-263THIN — reduced height.
• SOT-227 — large industrial isolated module (16 A class).
• DirectFET (International Rectifier, 2002) — copper-can flip-chip with large-area top contact for low Rds(on) and good thermals; widely used in VRMs for CPUs.
• PQFN-56 — 5×6 mm power QFN (Power-PAK 1212-8).
• Infineon TOLL (TO-Leadless) — leadless TO-220 cousin with very low parasitic inductance, used in 60–150 V automotive MOSFETs.
• Vishay PowerPAK SO-8 — exposed-pad SO-8 for trench MOSFETs.
• ON / Onsemi WPAK — leadless 5×6 mm.
• Toshiba DSOP-Advance — exposed-pad DSO with low Rds(on).

EV / industrial power modules

• Infineon EconoDUAL, EasyPACK (1B / 2B), HybridPACK 1/2/Drive — half-bridge or six-pack IGBT/SiC modules for traction inverters.
• Semikron SEMITOP, MiniSKiiP.
• Mitsubishi PM, J-Series IPMs.
• Wolfspeed (Cree) HPI / Easy-1B-SiC.
• Brick form factors: half-brick, quarter-brick, eighth-brick DC-DC modules.

11. RF and microwave packages

• Air-cavity ceramic — best for high-power RF (3–100 W amplifiers); cavity allows wire-bond inductance tuning, hermetic seal.
• Plastic flat-leadless QFN — low-cost consumer/comms RF up to ~6 GHz; widely used for Wi-Fi/BT/Zigbee front-ends.
• Copper-tungsten flange / copper-moly flange — bolt-down high-power packages with good thermal expansion match to BeO / AlN substrates; LDMOS power amps for base-stations.
• LGA-RF — Skyworks SkyOne FEM uses LGA for handset RF modules.
• QFN with cavity — for MEMS oscillators and small RF MEMS.
• Hermetic Kovar lid — Kovar (Fe-Ni-Co alloy) thermal-expansion-matched to glass; used in TO-5/TO-8 cans for crystal oscillators and high-rel space RF.

RF connectors (related to package interfaces)

• SMA — up to 18 GHz nominal, 26.5 GHz often usable.
• 3.5 mm — DC to 26.5 GHz.
• 2.92 mm (K-connector) — DC to 40 GHz.
• 2.4 mm — DC to 50 GHz.
• 1.85 mm (V-connector) — DC to 67 GHz.
• 1.0 mm — DC to 110 GHz.

12. Sensor and MEMS packages

• Open-cavity LGA / QFN — for pressure sensors, MEMS microphones, IMUs.
• Bosch BME280 — 2.5 × 2.5 × 0.93 mm metal-lid LGA-8, combined T/H/P sensor.
• ST LIS / LSM IMUs — typically LGA-12, LGA-14 (2.5 × 3.0 × 0.86 mm).
• Knowles / Goertek MEMS mics — bottom-port and top-port LGA with acoustic hole.
• Gel-fill or open-cavity for pressure sensors — direct media exposure for the diaphragm.
• Molded plastic with no cavity — for accelerometers / gyros that don’t need media access.
• Metal-lid hermetic — TO-5 / TO-8 / TO-39 cans for high-precision crystals, atomic-clock physics packages, photodiodes.

13. Module / SiP

• RF front-end modules (FEM) — Skyworks, Qorvo, Murata combine PA + LNA + switches + filters in one LGA or laminate-substrate package; ubiquitous in smartphones.
• GPS + IMU SiPs — ublox NEO-M9N, LEA-M8F; integrate GNSS RFIC + baseband + crystal in one module.
• Wi-Fi / Bluetooth SoC modules with shielded can — ESP32-WROOM-32 (Espressif), nRF7002-DK (Nordic), Murata Type 1MW; pre-certified for FCC/CE/IC, dramatically reducing OEM regulatory effort.
• Memory + SoC PoP — DRAM stacked on top of mobile AP, standard in smartphones from iPhone 4 through current.
• Power modules — TI µModule, Murata OKL DC-DC, Vicor BCM — buck/boost in a single package with embedded inductor.

14. JEDEC standard naming

JEDEC (Joint Electron Device Engineering Council, now JEDEC Solid State Technology Association) publishes mechanical outlines, reliability standards, and naming conventions.

• JEP95 — series of JEDEC publications defining package outlines.
• MO-### — Mechanical Outline (registered package).
• MS-### — Metal-can stand/standard (older outlines).
• Examples:
  • MO-220 — QFN family.
  • MO-153 — TSSOP.
  • MO-220 (W) — wettable-flank QFN.
  • MS-012 — SOIC narrow (3.9 mm body).
  • MS-013 — SOIC wide (7.5 mm body).
  • MO-137 — SSOP.
  • MS-026 — TQFP / LQFP.
  • MO-026 — QFP.
  • MO-187 — MSOP.

Manufacturers cross-reference internal codes (e.g., TI “DBV” = SOT-23-5, “RGE” = VQFN-24) to JEDEC outlines in their package mechanical drawings.

JEDEC also publishes JEDEC Solid State Product Outlines (JEP-95 sub-publications); IPC-7351 land-pattern recommendations are the corresponding PCB-side spec.

15. Pitch / size cheat sheet

Package	Pitch (mm)	Typ pin/ball count	Typ body size (mm)
DIP / PDIP	2.54	8 – 64	width 7.62 / 15.24
SDIP (shrink)	1.778	28 – 64	width 10.16
PGA	2.54 / 1.27	100 – 1000+	varies
TO-92	1.27	3	4.8 × 5.2
TO-220	2.54	3 / 5	10.0 × 15.5
TO-247	2.54	3	15.5 × 20.0
SOT-23	0.95	3	2.9 × 1.3
SOT-23-5/6	0.95	5 / 6	2.9 × 1.6
SC-70	0.65	3 – 6	2.0 × 1.25
SOIC narrow	1.27	8 – 16	3.9 wide
SOIC wide	1.27	16 – 32	7.5 wide
SSOP	0.635	8 – 56	5.3 wide
TSSOP	0.65	8 – 64	4.4 / 6.1 wide
MSOP-8/10	0.65	8 / 10	3.0 × 3.0
QSOP	0.635	16 – 28	3.9 wide
TQFP / LQFP	0.65 – 0.4	32 – 256	7×7 – 28×28
QFN	0.5 / 0.4	16 – 100	3×3 – 12×12
DFN-6 / DFN-8	0.5	6 / 8	2×2 – 3×3
BGA standard	1.0 / 0.8	64 – 2000+	7×7 – 50×50
FBGA	0.65 – 0.5	100 – 1000	8×8 – 20×20
MicroBGA / CSP	0.5 / 0.4	36 – 400	4×4 – 12×12
WLCSP	0.5 / 0.4 / 0.35	4 – 100	1×1 – 6×6
FCBGA (CPU)	1.0 / 0.8	1000 – 6000+	30×30 – 75×75
LGA (CPU)	1.0 / 0.8	775 – 6096	varies
DPAK (TO-252)	2.29	3	6.6 × 9.9
D²PAK (TO-263)	2.54	3 / 5	10.0 × 15.0
TOLL	1.27	8	9.9 × 11.7
SOT-227	n/a	4 (M5 studs)	31 × 47

16. Solder and reflow considerations

Leaded vs lead-free

• Pre-RoHS: tin-lead (Sn63/Pb37) eutectic, melting point 183 °C, reflow peak ~210–220 °C.
• Post-RoHS (1 July 2006, EU): lead-free, typically SAC305 (Sn96.5/Ag3.0/Cu0.5), melting ~217 °C, reflow peak 240–250 °C.
• Lead-free is mandatory for consumer in EU/CN; exemptions for aerospace, medical, military.

MSL — Moisture Sensitivity Level (J-STD-020)

• Level 1: unlimited floor life at ≤30 °C / 85 % RH.
• Level 2: 1 year.
• Level 2a: 4 weeks.
• Level 3: 168 hours (1 week).
• Level 4: 72 hours.
• Level 5: 48 hours.
• Level 5a: 24 hours.
• Level 6: time-on-label (typically 6 hours) — must reflow immediately after pre-bake.
• Above MSL 1, parts must be dry-baked (typically 125 °C, 24–96 hours) if floor life is exceeded; failure to bake causes “popcorn” delamination during reflow.

Surface finishes (PCB side)

• HASL — Hot-Air Solder Level — cheap, lead-free or leaded; uneven surface, less good for fine-pitch.
• ENIG — Electroless Nickel / Immersion Gold — flat, good for BGA/QFN; risk of “black pad”.
• ENEPIG — Electroless Nickel / Electroless Palladium / Immersion Gold — better for wire-bonding.
• OSP — Organic Solderability Preservative — cheap, single-reflow.
• Immersion silver / tin — alternatives.

Package-specific

• BGA — solder paste optional (balls reflow themselves); X-ray inspection or AOI of edges; reballing kits exist for rework.
• QFN — solder paste stencil 100–125 µm; exposed pad needs vias to inner plane or back-side copper for thermal; window-pane stencil aperture for the thermal pad prevents float.
• WLCSP — tight stencil (75 µm), strong flux, careful reflow; often underfilled for board-level reliability.
• LGA — paste + careful placement; pin-on-paste for socketed parts.

17. Reliability

JEDEC reliability standards

• JESD22-A104 — Temperature Cycling (TC): -55 to +125 °C, 1000 cycles common.
• JESD22-A101 — Steady-State Temperature/Humidity Bias Life (HTRB).
• JESD22-A102 — Accelerated Moisture Resistance (AMR).
• JESD22-A110 — Highly Accelerated Stress Test (HAST), 130 °C / 85 % RH.
• JESD22-B101 — Mechanical Shock.
• JESD22-B103 — Vibration.
• J-STD-020 — MSL classification.
• JEP122 — Failure mechanisms and models for semiconductors.

AEC-Q100 (automotive grades)

• Grade 0: ambient operating -40 to +150 °C.
• Grade 1: -40 to +125 °C.
• Grade 2: -40 to +105 °C.
• Grade 3: -40 to +85 °C.
• AEC-Q200 — equivalent for passives.
• AEC-Q101 — discrete semiconductors.
• AEC-Q104 — multi-chip modules.

Special concerns

• BGA solder-joint fatigue under TC — Coffin-Manson model; underfill mitigates.
• Whisker growth on pure-Sn surfaces (long-term reliability risk for high-rel) — JESD201A defines acceptance criteria.
• Black pad on ENIG — Ni-P corrosion under Au.
• Conductive anodic filaments (CAF) at high humidity and voltage between BGA vias.

18. Selection heuristics

• Quick prototype, hand-solder, hobbyist → DIP or SOIC (wide pitch, easy iron).
• Cost-sensitive consumer, machine-assembled → QFN, DFN, SOIC, or CSP.
• High pin-count digital (FPGA, AP, MCU > 200 pins) → BGA / FBGA; LGA for sockets.
• Thermal-sensitive power (>1 W dissipation) → exposed-pad QFN, DPAK, D²PAK, TO-220, or TO-247; consider top-side cooled (DirectFET, TOLL).
• Automotive → AEC-Q100 + extended-temperature package + wettable-flank QFN for AOI.
• mm-wave RF (>30 GHz) → air-cavity QFN, chip-on-board, or flip-chip on RF laminate.
• High-speed memory (DDR4/DDR5, HBM) → BGA with matched-trace and reference-plane stackup; HBM uses 2.5D interposer.
• Mobile, space-constrained → WLCSP or fan-out (InFO).
• Ultra-fine I/O density (>2000 I/O at fine pitch) → flip-chip BGA, 2.5D interposer, or chiplet via UCIe.
• High-reliability (space, military) → hermetic ceramic (CDIP, CBGA, TO-can) with full screening (MIL-PRF-38535 class V, MIL-PRF-38534 class H/K).

19. Cross-references

• semiconductor-materials — die materials (Si, SiC, GaN, GaAs, InP).
• passive-components — companion R/L/C package sizes and AEC-Q200.
• connector-families — board-to-board, board-to-wire, RF connectors.
• pcb-design — layout rules for QFN thermal pad, BGA escape routing, controlled-impedance stackups.
• pcb-substrates — FR-4, high-Tg, Rogers, ceramic substrates.

20. Citations and references

• JEDEC JEP95 series — JEDEC Registered and Standard Outlines for Solid State and Related Products. https://www.jedec.org/
• JEDEC JESD22 — Reliability Test Methods for Packaged Devices.
• IPC J-STD-020 — Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices.
• IPC-7351 — Generic Requirements for Surface Mount Design and Land Pattern Standard.
• AEC-Q100 / Q101 / Q104 — Automotive Electronics Council qualification standards.
• Tummala, R. R. Fundamentals of Microsystems Packaging, 2nd ed., McGraw-Hill, 2019.
• Lau, J. H. Fan-Out Wafer-Level Packaging, Springer, 2018.
• Lau, J. H. 3D IC Integration and Packaging, McGraw-Hill, 2016.
• TSMC 3DFabric technical briefs — InFO, CoWoS, SoIC.
• UCIe Specification 1.0 (2022) and 2.0 (2024). https://www.uciexpress.org/
• MIL-PRF-38535 — Integrated Circuits Manufacturing General Specification.